Specifications
| Type | Description |
|---|---|
| Part Number | AD7402-8BRIZ-RL7 |
| Manufacturer | Analog Devices |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 8-lead wide-body SOIC with increased creepage, RI-8-1 package |
| Resolution | 16 bits; filter output truncated to 16 bits |
| Internal Clock Rate | 10 MHz; internal clock |
| Master Clock Output Frequency | 9.4 MHz min, 10 MHz typ, 10.6 MHz max; VDD1=4.5 V to 5.5 V, VDD2=3 V to 5.5 V, TA=-40°C to +105°C |
| Integral Nonlinearity | ±1 LSB typ, ±5 LSB max; tested with sinc3 filter, 256 decimation rate |
| Differential Nonlinearity | ±0.99 LSB max; guaranteed no missed codes to 16 bits |
| Offset Error | ±0.2 mV typ, ±0.75 mV max; VIN+=-250 mV to +250 mV, VIN-=0 V |
| Offset Drift vs Temperature | 1.7 µV/°C typ, 5 µV/°C max; TA=-40°C to +105°C |
| Offset Drift vs VDD1 | 85 µV/V typ; VDD1 variation |
| Gain Error | 0.2% FSR typ, ±0.5% FSR max; tested with sinc3 filter, 256 decimation rate |
| Gain Error Drift vs Temperature | 18 ppm/°C typ, 32 ppm/°C max; 11 µV/°C typ, 20 µV/°C max; TA=-40°C to +105°C |
| Gain Error Drift vs VDD1 | 0.2 mV/V typ; VDD1 variation |
| Analog Input Voltage Range | -320 mV min, +320 mV max; differential full-scale analog input range |
| Nominal Differential Input Signal Range | ±250 mV; general operating input signal |
| Input Common-Mode Voltage Range | -200 mV to +300 mV; analog input |
| Dynamic Input Current | ±19 µA typ, ±28 µA max; VIN+=±250 mV, VIN-=0 V |
| Dynamic Input Current | 0.05 µA typ; VIN+=0 V, VIN-=0 V |
| Input Capacitance | 14 pF typ; analog input |
| SINAD | 74 dB min, 82 dB typ; VIN+=35 Hz, sinc3 filter, 256 decimation rate |
| Signal-to-Noise Ratio | 86 dB min, 87 dB typ; VIN+=35 Hz, sinc3 filter, 256 decimation rate |
| Total Harmonic Distortion | -84 dB typ; VIN+=35 Hz, sinc3 filter, 256 decimation rate |
| Spurious-Free Dynamic Range | -84 dB typ; peak harmonic or spurious noise |
| Effective Number of Bits | 12 bits min, 13.5 bits typ; VIN+=35 Hz, sinc3 filter, 256 decimation rate |
| Noise Free Code Resolution | 14 bits typ; VIN+=35 Hz, sinc3 filter, 256 decimation rate |
| Isolation Transient Immunity | 25 kV/µs min, 30 kV/µs typ; common-mode transient immunity |
| Output High Voltage | VDD2 - 0.1 V min; IO=-200 µA |
| Output Low Voltage | 0.4 V max; IO=+200 µA |
| VDD1 Supply Voltage | 4.5 V min, 5.5 V max; power requirements |
| VDD2 Supply Voltage | 3 V min, 5.5 V max; power requirements |
| VDD1 Supply Current | 26 mA typ, 31 mA max; VDD1=5.5 V |
| VDD2 Supply Current | 6 mA typ, 7 mA max; VDD2=5.5 V |
| VDD2 Supply Current | 4.5 mA typ, 5.5 mA max; VDD2=3.3 V |
| Power Dissipation | 209 mW typ; VDD1=VDD2=5.5 V |
| Data Access Time After MCLKOUT Rising Edge | ±10 ns max; measured with ±200 µA load and 25 pF load capacitance |
| Data Hold Time After MCLKOUT Falling Edge | 44 ns max; measured with ±200 µA load and 25 pF load capacitance |
| Master Clock Low Time | 33 ns min; clock output mark-space ratio 45/55 to 55/45 |
| Master Clock High Time | 33 ns min; clock output mark-space ratio 45/55 to 55/45 |
| Input-to-Output Resistance | 10^12 Ω typ; pins 1-4 shorted together and pins 5-8 shorted together |
| Input-to-Output Capacitance | 2.2 pF typ; f=1 MHz |
| Junction-to-Ambient Thermal Resistance | 105 °C/W typ; thermocouple at center of package underside, 4-layer board with thin traces |
| Input-to-Output Momentary Withstand Voltage | 5000 V rms min; 1-minute duration |
| Minimum External Air Gap | 8.1 mm min; clearance from input terminals to output terminals through air |
| Minimum External Tracking | 8.1 mm min; creepage from input terminals to output terminals along body |
| Minimum Internal Gap | 0.034 mm min; insulation distance through insulation |
| Comparative Tracking Index | >400 V; DIN IEC 112/VDE 0303 Part 1 |
| Isolation Group | Group II; material group per DIN VDE 0110, 1/89, Table I |
| UL Isolation Voltage | 5000 V rms; UL 1577, single protection |
| VDE Maximum Working Insulation Voltage | 1250 VPEAK; reinforced insulation per DIN V VDE V 0884-10:2006-12 |
| CSA Basic Insulation Maximum Working Voltage | 810 V rms, 1145 VPEAK; CSA 60950-1-07 and IEC 60950-1, pollution degree 2, Material Group III calculation |
| CSA Reinforced Insulation Maximum Working Voltage | 405 V rms, 583 VPEAK; CSA 60950-1-07 and IEC 60950-1, pollution degree 2, Material Group III calculation |
| IEC 60601-1 Reinforced Insulation Maximum Working Voltage | 250 V rms, 353 VPEAK; reinforced insulation per IEC 60601-1 |
| Pollution Degree | 2; DIN VDE 0110, Table 1 |
| Climatic Classification | 40/105/21; DIN V VDE V 0884-10 insulation characteristics |
| Input-to-Output Test Voltage Method B1 | 2344 VPEAK; VIORM x 1.875 = VPR, 100% production test, tm=1 s, partial discharge <5 pC |
| Input-to-Output Test Voltage Method A Subgroup 1 | 2000 VPEAK; after environmental test subgroup 1, VIORM x 1.6 = VPR, tm=60 s, partial discharge <5 pC |
| Input-to-Output Test Voltage Method A Subgroup 2/3 | 1500 VPEAK; after input and/or safety test subgroup 2/safety test subgroup 3, VIORM x 1.2 = VPR, tm=60 s, partial discharge <5 pC |
| Highest Allowable Overvoltage | 8000 VPEAK; transient overvoltage, t=10 s |
| Surge Isolation Voltage | 12000 VPEAK; 1.2 µs rise time, 50 µs to 50% fall time |
| Safety Limiting Case Temperature | 150°C; maximum value allowed in failure event |
| Safety Limiting Power Dissipation | 1.19 W; Side 1 and Side 2 power dissipation maximum in failure event |
| Insulation Resistance | >10^9 Ω; TS, VIO=500 V |
| VDD1 Absolute Maximum Rating | -0.3 V to +6.5 V; relative to GND1 |
| VDD2 Absolute Maximum Rating | -0.3 V to +6.5 V; relative to GND2 |
| Analog Input Voltage Absolute Maximum Rating | -1 V to VDD1 + 0.3 V; relative to GND1 |
| Output Voltage Absolute Maximum Rating | -0.3 V to VDD2 + 0.3 V; relative to GND2 |
| Input Current Absolute Maximum Rating | ±10 mA; any pin except supplies; transient currents up to 100 mA do not cause SCR latch-up |
| Operating Temperature Range | -40°C to +105°C; functional operating range |
| Storage Temperature Range | -65°C to +150°C; absolute maximum rating |
| Junction Temperature | 150°C; absolute maximum rating |
| Pb-Free Reflow Temperature | 260°C; soldering reflow |
| ESD Rating | 2 kV; absolute maximum ratings table |
| FICDM ESD Rating | ±1250 V; JESD22-C101, RC network 1 Ω, package capacitance, Class IV |
| HBM ESD Rating | ±4000 V; ESDA/JEDEC JS-001-2011, RC network 1.5 kΩ and 100 pF, Class 3A |
| Maximum Continuous Working Voltage | 1250 VPEAK; AC bipolar waveform, 20-year minimum lifetime, VDE approved working voltage |
| Maximum Continuous Working Voltage | 1250 VPEAK; AC unipolar waveform, 20-year minimum lifetime |
| Maximum Continuous Working Voltage | 1250 VPEAK; DC voltage, 20-year minimum lifetime |
| Datasheet Status | request_only |
Product Overview
The modulator uses an internal 10 MHz clock and specifies a master clock output frequency of 9.4 MHz minimum, 10 MHz typical, and 10.6 MHz maximum across VDD1 from 4.5 V to 5.5 V, VDD2 from 3 V to 5.5 V, and -40°C to +105°C ambient temperature. With a sinc3 filter and 256 decimation rate, extracted performance includes ±1 LSB typical integral nonlinearity, ±0.99 LSB maximum differential nonlinearity, 86 dB minimum signal-to-noise ratio, and 12-bit minimum effective number of bits.
Key Features
- 16-bit filter output truncation
- Internal 10 MHz clock operation
- ±250 mV nominal differential input range
- -320 mV to +320 mV full-scale analog input range
- 86 dB minimum signal-to-noise ratio
- 74 dB minimum SINAD with sinc3 filtering
- 25 kV/µs minimum common-mode transient immunity
- 5000 V rms input-to-output withstand voltage
- 8.1 mm minimum clearance and creepage
- -40°C to +105°C operating temperature range
- VDD1 4.5 V to 5.5 V supply range
- VDD2 3 V to 5.5 V supply range
Typical Applications
- Isolated analog signal measurement
- Current shunt measurement interfaces
- Sigma-delta data acquisition channels
- High common-mode transient environments
- Reinforced insulation signal paths
- Medical insulation barrier designs
- Industrial control signal isolation
Procurement Notes
When requesting a quote for AD7402-8BRIZ-RL7, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is AD7402-8BRIZ-RL7?
AD7402-8BRIZ-RL7 is an Analog Devices isolated sigma-delta modulator in the Signal_Chain category. The extracted package data identifies it as an 8-lead wide-body SOIC with increased creepage, RI-8-1 package.
What input signal range does this modulator support?
The nominal differential input signal range is ±250 mV. The extracted full-scale analog input range is -320 mV minimum to +320 mV maximum, with an input common-mode voltage range from -200 mV to +300 mV.
What clocking parameters are specified for AD7402-8BRIZ-RL7?
The device has an internal 10 MHz clock. Its master clock output frequency is specified as 9.4 MHz minimum, 10 MHz typical, and 10.6 MHz maximum across the listed VDD1, VDD2, and temperature conditions.
What isolation ratings are listed for this part?
Extracted isolation data includes 5000 V rms minimum input-to-output momentary withstand voltage, 25 kV/µs minimum common-mode transient immunity, 8.1 mm minimum external clearance, and 8.1 mm minimum external creepage.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: August 17, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.