Specifications
| Type | Description |
|---|---|
| Part Number | DAC60502 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 10-pin WSON (DRX), 2.50 mm x 2.50 mm body |
| Component Type | Other |
| Resolution | 12 bits; condition: DAC60502 device variant |
| Number of DAC channels | 2 channels; condition: Dual DAC device family |
| Integral nonlinearity (INL) | -1 to +1 LSB; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V, DAC output range >= 2.5 V |
| Differential nonlinearity (DNL) | -1 to +1 LSB; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V, DAC output range >= 2.5 V |
| Total unadjusted error (TUE) | min -0.1, typ 0.04, max 0.1 %FSR; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V |
| Zero code error | min -1.5, typ 0.5, max 1.5 mV; condition: DAC loaded with zero-scale code |
| Zero code error temperature coefficient | typ ±2 µV/°C; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V |
| Offset error | min -1.5, typ 0.5, max 1.5 mV; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V |
| Offset error temperature coefficient | typ ±2 µV/°C; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V |
| Gain error | min -0.1, typ 0.04, max 0.1 %FSR; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V |
| Gain error temperature coefficient | typ ±1 ppm FSR/°C; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V |
| Full-scale error | min -0.1, typ 0.04, max 0.1 %FSR; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V |
| Full-scale error temperature coefficient | typ ±2 ppm FSR/°C; condition: TA=-40°C to +125°C, 2.7 V <= VDD <= 5.5 V |
| Supply voltage | 2.7 to 5.5 V; condition: Recommended operating condition, VDD to AGND |
| Operating temperature | -40°C to +125°C; condition: Recommended operating free-air temperature |
| Digital input high voltage | min 1.62 V; condition: Recommended operating condition |
| Digital input low voltage | max 0.45 V; condition: Recommended operating condition |
| Buffered output voltage range | 0 to 2 x VREFIO; condition: BUFF-GAIN bit = 1, REF-DIV bit = 0 |
| Buffered output voltage range | 0 to VREFIO; condition: BUFF-GAIN bit = 1, REF-DIV bit = 1 |
| Buffered output voltage range | 0 to 0.5 x VREFIO; condition: BUFF-GAIN bit = 0, REF-DIV bit = 1 |
| Resistive load | min 0.25 kΩ; condition: VDD = 2.7 V |
| Resistive load | min 0.5 kΩ; condition: VDD = 5.5 V |
| Capacitive load | max 2 nF; condition: RLOAD = infinite |
| Capacitive load | max 10 nF; condition: RLOAD = 2 kΩ |
| Load regulation | typ 80 µV/mA; condition: DAC at midscale, -10 mA <= IOUT <= 10 mA |
| Short-circuit current | typ 30 mA per channel; condition: Full-scale output shorted to AGND |
| Short-circuit current | typ 30 mA per channel; condition: Zero output shorted to VDD |
| Output voltage headroom | typ 0.3 V, max 0.1 V as listed; condition: To VDD, DAC at full code, IOUT = 10 mA sourcing |
| Output voltage footroom | typ 0.3 V; condition: To AGND, DAC at zero code, IOUT = 10 mA sinking |
| DC small-signal output impedance | typ 0.1 Ω; condition: DAC at midscale |
| DC small-signal output impedance | typ 10 Ω; condition: DAC at code 256 |
| DC small-signal output impedance | typ 10 Ω; condition: DAC at code 65279 |
| Power-supply rejection ratio, DC | typ 0.15 mV/V; condition: DAC at midscale, VDD = 5 V ±10% |
| Output voltage drift vs time | typ 20 ppm of FSR; condition: TA = 35°C, VOUT = midscale, 1900 hr |
| Reference input impedance | typ 100 kΩ; condition: VREFIO pin |
| Reference input capacitance | typ 5 pF; condition: VREFIO pin |
| Internal reference output voltage | min 2.4975 V, max 2.5025 V; condition: TA = 25°C |
| Internal reference output drift | typ 10 ppm/°C; condition: DAC70502 and DAC60502 |
| Internal reference output impedance | typ 0.1 Ω; condition: Voltage reference output |
| Internal reference output noise | typ 14 µVPP; condition: 0.1 Hz to 10 Hz |
| Internal reference output noise density | typ 140 nV/√Hz; condition: Measured at 10 kHz, reference load = 10 nF |
| Internal reference load current | ±5 mA; condition: Voltage reference output |
| Internal reference load regulation | typ 90 µV/mA; condition: Sourcing and sinking |
| Internal reference line regulation | typ 20 µV/V; condition: Voltage reference output |
| Reference output voltage drift vs time | typ 20 µV; condition: TA = 35°C, 1900 hr |
| Reference thermal hysteresis | typ 480 ppm; condition: 1st cycle |
| Reference thermal hysteresis | typ 25 ppm; condition: Additional cycle |
| Output voltage settling time | typ 5 µs; condition: 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V |
| Output voltage settling time | typ 3 µs; condition: 10 mV settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V |
| Slew rate | typ 2 V/µs; condition: VDD = 5.5 V, VREFIO = 2.5 V |
| Power-on glitch magnitude | typ 200 mV; condition: CLOAD = 50 pF |
| Output noise | typ 14 µVPP; condition: 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V |
| Output noise | typ 23 µVrms; condition: 100 kHz bandwidth, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V |
| Output noise density | typ 78 nV/√Hz; condition: Measured at 1 kHz, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V, gain = 2x |
| Output noise density | typ 74 nV/√Hz; condition: Measured at 10 kHz, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V, gain = 2x |
| Output noise density | typ 55 nV/√Hz; condition: Measured at 1 kHz, DAC at full scale, VDD = 2.7 V, external VREFIO = 2.5 V, gain = 1x |
| Output noise density | typ 50 nV/√Hz; condition: Measured at 10 kHz, DAC at full scale, VDD = 2.7 V, external VREFIO = 2.5 V, gain = 1x |
| Spurious-free dynamic range | typ 70 dB; condition: 1 kHz sinusoid at DAC output, DAC updated at 500 kHz, includes up to 7th harmonics, no filter on DAC output |
| Total harmonic distortion | typ 70 dB; condition: 1 kHz sinusoid at DAC output, DAC updated at 500 kHz, includes up to 7th harmonics, no filter on DAC output |
| Serial interface modes | SPI or I2C; condition: Selected by SPI2C pin; pin must remain static after power-up |
| SPI clock rate | up to 50 MHz; condition: 3-wire SPI-compatible mode |
| I2C supported speeds | 100 kbps, 400 kbps, 1.0 Mbps; condition: Standard, fast, and fast-mode plus I2C modes |
| Power-on reset output state | zero scale or midscale; condition: Selected by RSTSEL pin; zero scale if RSTSEL = AGND, midscale if RSTSEL = VDD |
| Absolute maximum supply voltage | -0.3 to 6 V; condition: VDD to AGND |
| Absolute maximum VREFIO voltage | -0.3 to VDD + 0.3 V; condition: VREFIO to AGND |
| Absolute maximum digital input voltage | -0.3 to VDD + 0.3 V; condition: Digital inputs to AGND |
| Absolute maximum output voltage | -0.3 to VDD + 0.3 V; condition: VOUTx to AGND |
| Absolute maximum input current | -10 to +10 mA; condition: Current into any pin |
| Junction temperature range | -40°C to +150°C; condition: Absolute maximum rating |
| Storage temperature range | -65°C to +150°C; condition: Absolute maximum rating |
| ESD rating, human body model | ±2000 V; condition: Per ANSI/ESDA/JEDEC JS-001, all pins |
| ESD rating, charged device model | ±1000 V; condition: Per JEDEC JESD22-C101, all pins |
| Junction-to-ambient thermal resistance | 99.7°C/W; condition: DRX WSON, 10 pins |
| Junction-to-case top thermal resistance | 49.9°C/W; condition: DRX WSON, 10 pins |
| Junction-to-board thermal resistance | 35.9°C/W; condition: DRX WSON, 10 pins |
| Datasheet Status | request_only |
Product Overview
The DAC60502 is a Texas Instruments dual 12-bit voltage-output DAC for Signal_Chain designs that need two programmable analog voltage outputs. It operates from a 2.7 V to 5.5 V supply across a recommended free-air temperature range of -40°C to +125°C, with digital input thresholds of at least 1.62 V for high and up to 0.45 V for low.
Static accuracy specifications include -1 to +1 LSB integral and differential nonlinearity under the stated supply, temperature, and output-range conditions. Total unadjusted error, gain error, and full-scale error are specified from -0.1%FSR to +0.1%FSR, with typical values of 0.04%FSR. The device includes an internal reference with 2.4975 V to 2.5025 V output at 25°C and 10 ppm/°C typical drift for DAC60502.
The output buffer supports selectable ranges of 0 to 2 x VREFIO, 0 to VREFIO, or 0 to 0.5 x VREFIO depending on BUFF-GAIN and REF-DIV settings. Serial control is through SPI or I2C selected by the SPI2C pin, and the package is a compact 10-pin WSON (DRX), 2.50 mm x 2.50 mm body.
Key Features
- Dual 12-bit voltage-output DAC with two channels
- 2.7 V to 5.5 V recommended supply range
- -40°C to +125°C recommended operating temperature
- INL and DNL specified from -1 to +1 LSB
- SPI or I2C interface selected by SPI2C pin
- SPI-compatible mode supports clock rates up to 50 MHz
- I2C supports 100 kbps, 400 kbps, and 1.0 Mbps
- Selectable reset output state: zero scale or midscale
- Internal reference specified from 2.4975 V to 2.5025 V
- 10-pin WSON package with 2.50 mm x 2.50 mm body
Typical Applications
- Dual-channel analog voltage output
- SPI-controlled signal-chain outputs
- I2C-controlled signal-chain outputs
- Reference-based programmable output ranges
- Low-voltage DAC output control
- Temperature-rated analog control circuits
Procurement Notes
When requesting a quote for DAC60502, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What resolution does the DAC60502 provide?
The DAC60502 device variant provides 12-bit resolution. It is part of a dual DAC device family, so the extracted datasheet facts identify two DAC channels for voltage-output signal-chain use.
What supply and temperature range are specified?
The recommended operating supply range is 2.7 V to 5.5 V from VDD to AGND. The recommended operating free-air temperature range is -40°C to +125°C.
Which serial interfaces are supported by DAC60502?
The serial interface mode is selected by the SPI2C pin, which must remain static after power-up. The extracted facts list SPI or I2C, with SPI up to 50 MHz and I2C at 100 kbps, 400 kbps, or 1.0 Mbps.
What output ranges can the buffered DAC output use?
The buffered output range depends on BUFF-GAIN and REF-DIV settings. Listed ranges are 0 to 2 x VREFIO, 0 to VREFIO, and 0 to 0.5 x VREFIO under the stated bit configurations.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.