Specifications
| Type | Description |
|---|---|
| Part Number | DP83867IS |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package Case | RGZ, 48-pin VQFN, 7 mm x 7 mm |
| Supported Ethernet Protocols | 10BASE-Te, 100BASE-TX, 1000BASE-T; IEEE 802.3 compatible |
| MAC Interface Options | RGMII, SGMII; interface to MAC layer |
| Transmit Latency | < 90 ns; TX path |
| Receive Latency | < 290 ns; RX path |
| Power Consumption | 457 mW; full operating power |
| ESD Protection | > 8000 V; IEC 61000-4-2 direct contact |
| Emission Compliance | EN55011 Class B |
| RGMII Delay Modes | 16 programmable modes; RX and TX |
| I/O Voltage Options | 3.3 V, 2.5 V, 1.8 V; configurable I/O voltage |
| Clock Output Frequencies | 25 MHz or 125 MHz; synchronized clock output |
| Reference Clock Input | 25 MHz; crystal or oscillator input |
| Reference Clock Tolerance | 50 ppm; 25 MHz oscillator or crystal input on XI |
| Temperature Range | -40°C to +85°C; DP83867ISRGZ industrial grade |
| Temperature Grade | Industrial; DP83867ISRGZ |
| Orderable Package | DP83867ISRGZ; industrial temperature version |
| Package Pin Count | 48 pins; RGZ VQFN package |
| Package Dimensions | 7 mm x 7 mm; RGZ VQFN package nominal size |
| RGMII Transmit Clock Frequency | 125 MHz nominal; GTX_CLK sourced from MAC to PHY |
| RGMII Receive Clock Frequency at 10 Mbps | 2.5 MHz |
| RGMII Receive Clock Frequency at 100 Mbps | 25 MHz |
| RGMII Receive Clock Frequency at 1000 Mbps | 125 MHz |
| SGMII Clock Output Frequency | 625 MHz; differential SGMII clock output driven by PHY |
| SGMII AC Coupling Capacitor | 0.1 µF; SGMII input/output connection to MAC |
| MDC Maximum Clock Rate | 25 MHz; MDIO serial management clock |
| MDC Minimum Clock Rate | No minimum; MDIO serial management clock |
| MDIO Pullup Resistor | 1.5 kΩ specified, 2.2 kΩ acceptable; MDIO bidirectional management pin |
| Interrupt Pullup Resistor | 2.2 kΩ; INT/PWDN used as open-drain interrupt, connected to VDDIO |
| Reset Pulse Width | Minimum 1 µs; RESET_N held low |
| JTAG Clock Maximum Frequency | 2.5 MHz; JTAG_CLK IEEE 1149.1 test clock input |
| JTAG Reset Sequence | 3 clock cycles; JTAG_TMS high to reset JTAG |
| Datasheet Status | request_only |
Product Overview
The DP83867IS is a Texas Instruments Ethernet PHY transceiver in the Signal_Chain category. It is IEEE 802.3 compatible for 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet operation, with MAC layer interface options for RGMII and SGMII.
For timing-sensitive designs, the device specifies less than 90 ns transmit latency and less than 290 ns receive latency. RGMII operation includes 16 programmable RX and TX delay modes, a 125 MHz nominal transmit clock from the MAC to the PHY, and receive clock frequencies of 2.5 MHz, 25 MHz, or 125 MHz depending on 10 Mbps, 100 Mbps, or 1000 Mbps mode.
The DP83867ISRGZ orderable package is the industrial temperature version, rated from -40°C to +85°C. It uses the RGZ 48-pin VQFN package with a 7 mm x 7 mm nominal body size. Interface support includes configurable 3.3 V, 2.5 V, or 1.8 V I/O voltage, MDIO management up to a 25 MHz MDC clock, a 25 MHz reference clock input with 50 ppm tolerance, and synchronized 25 MHz or 125 MHz clock output.
Key Features
- IEEE 802.3 compatible 10BASE-Te, 100BASE-TX, 1000BASE-T support
- RGMII and SGMII MAC layer interface options
- Transmit latency below 90 ns on TX path
- Receive latency below 290 ns on RX path
- 457 mW full operating power consumption
- More than 8000 V IEC 61000-4-2 direct contact ESD
- EN55011 Class B emissions compliance
- Sixteen programmable RGMII RX and TX delay modes
- Configurable 3.3 V, 2.5 V, or 1.8 V I/O
- Industrial -40°C to +85°C DP83867ISRGZ temperature range
Typical Applications
- 10BASE-Te Ethernet PHY links
- 100BASE-TX Ethernet PHY links
- 1000BASE-T Ethernet PHY links
- RGMII MAC-to-PHY interfaces
- SGMII MAC-to-PHY interfaces
- MDIO-managed Ethernet designs
- Industrial temperature Ethernet equipment
- JTAG-tested network hardware
Procurement Notes
When requesting a quote for DP83867IS, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What Ethernet protocols does DP83867IS support?
DP83867IS supports IEEE 802.3 compatible 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet operation. It is identified as an Ethernet PHY transceiver for MAC-to-physical-layer interface designs.
Which MAC interfaces are available on DP83867IS?
The extracted datasheet facts list RGMII and SGMII as MAC layer interface options. RGMII includes programmable RX and TX delay modes, while SGMII uses a differential 625 MHz clock output from the PHY.
What package is used for the DP83867ISRGZ version?
The DP83867ISRGZ orderable package is the industrial temperature version in an RGZ 48-pin VQFN package. The nominal package size is 7 mm x 7 mm.
What reference clock does DP83867IS require?
DP83867IS uses a 25 MHz crystal or oscillator reference clock input. The extracted facts specify 50 ppm tolerance for the 25 MHz oscillator or crystal input on XI.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.