Specifications
| Type | Description |
|---|---|
| Part Number | DRV8412 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Component Type | Power_IC |
| Package / Case | HTSSOP (DDW), 44 pins, 14 mm x 8.1 mm |
| Output Configuration | Dual full-bridge or four half-bridge motor driver |
| Maximum Operating Supply Voltage | 52 V, PVDD supply |
| Recommended PVDD_X Supply Voltage | 0 to 52.5 V, half bridge X DC supply voltage |
| Nominal PVDD Supply Voltage | 50 V, typical operating supply for PVDD |
| Recommended GVDD_X Supply Voltage | 10.8 min, 12 typ, 13.2 max V |
| Recommended VDD Supply Voltage | 10.8 min, 12 typ, 13.2 max V |
| Continuous Output Current | 2 x 3 A, DRV8412 dual full-bridge mode |
| Peak Output Current | 2 x 6 A, DRV8412 dual full-bridge mode |
| Parallel Mode Continuous Current | 6 A, DRV8412 parallel mode |
| Parallel Mode Peak Current | 12 A, DRV8412 parallel mode |
| Recommended Pulsed Peak Current | 15 A per output pin, may be thermally limited |
| Absolute Maximum Transient Peak Output Current | 16 A per pin, pulse width limited by internal overcurrent protection circuit |
| Absolute Maximum Transient Peak Output Current for Latch Shutdown | 20 A per pin |
| PWM Switching Frequency | 500 kHz max, recommended operating condition |
| Efficiency | Up to 97%, power stage efficiency |
| MOSFET RDS(on) | 110 mOhm, TJ = 25°C |
| VDD Absolute Maximum Voltage | -0.3 to 13.2 V, VDD to GND |
| GVDD_X Absolute Maximum Voltage | -0.3 to 13.2 V, GVDD_X to GND |
| PVDD_X Absolute Maximum Voltage | -0.3 to 70 V, PVDD_X to GND_X; transient spikes only |
| OUT_X Absolute Maximum Voltage | -0.3 to 70 V, OUT_X to GND_X; transient spikes only |
| BST_X Absolute Maximum Voltage | -0.3 to 80 V, BST_X to GND_X; transient spikes only |
| VREG Absolute Maximum Voltage | -0.3 to 4.2 V, VREG to AGND |
| PWM_X Input Absolute Maximum Voltage | -0.3 to VREG + 0.5 V, PWM_X to GND |
| RESET_X, FAULT, OTW Absolute Maximum Voltage | -0.3 to 7 V, RESET_X, FAULT, OTW to GND |
| FAULT and OTW Continuous Sink Current | 9 mA max, open-drain outputs |
| Operating Junction Temperature | -40 to 150°C, absolute maximum rating |
| Storage Temperature | -55 to 150°C, absolute maximum rating |
| Operating Ambient Temperature | -40 to 85°C, recommended operating condition |
| ESD Rating | ±1500 V, charged device model, all pins, JEDEC JESD22-C101 |
| Cycle-by-Cycle OC Programming Resistor Range | 24 to 200 kOhm, cycle-by-cycle current limit modes |
| OC Latching Shutdown Programming Resistor Range | 22 to 200 kOhm, OC latching shutdown modes |
| Bootstrap Capacitor Range | 33 to 220 nF, CBST |
| Minimum PWM Pulse Duration | 50 ns, low side on-time for charging bootstrap capacitor |
| VREG Output Voltage | 2.95 min, 3.3 typ, 3.65 max V; VDD = 12 V |
| VDD Supply Current, Idle | 9 typ, 12 max mA, reset mode |
| VDD Supply Current, Operating | 10.5 mA typ, 50% duty cycle |
| Gate Supply Current per Half-Bridge, Reset | 1.7 typ, 2.5 max mA |
| Gate Supply Current per Half-Bridge, Operating | 8 mA typ, 50% duty cycle |
| PVDD Half-Bridge Idle Current | 0.7 typ, 1 max mA, reset mode |
| DRV8412 Junction-to-Ambient Thermal Resistance | 24.5°C/W, DDW package |
| DRV8412 Junction-to-Case Top Thermal Resistance | 7.8°C/W, DDW package |
| DRV8412 Junction-to-Board Thermal Resistance | 5.5°C/W, DDW package |
| DRV8412 Junction-to-Case Bottom Thermal Resistance | 0.2°C/W, DDW package |
| DRV8412 Package Heat Dissipation RθJC | 1.1°C/W, junction-to-case, power pad |
| DRV8412 Package Heat Dissipation RθJA | 25°C/W, junction-to-ambient |
| Exposed Power Pad Area | 34 mm2, DRV8412 package |
| Package Power Rating at TA = 25°C | 5.0 W, DRV8412 44-pin TSSOP DDW, based on EVM board layout |
| Package Power Derating Factor | 40.0 mW/°C above TA = 25°C |
| Package Power Rating at TA = 70°C | 3.2 W, DRV8412 44-pin TSSOP DDW |
| Package Power Rating at TA = 85°C | 2.6 W, DRV8412 44-pin TSSOP DDW |
| Package Power Rating at TA = 125°C | 1.0 W, DRV8412 44-pin TSSOP DDW |
| Protection Features | Undervoltage, overtemperature, overload, and short-circuit protection |
| Current Limit Feature | Programmable cycle-by-cycle current limit using OC_ADJ resistor |
| FAULT Output Type | Open-drain, active-low, internal pullup to VREG 3.3 V |
| OTW Output Type | Open-drain, active-low, internal pullup to VREG 3.3 V |
| Mode 000 Configuration | 2 full bridges or 4 half bridges; M3=0, M2=0, M1=0; cycle-by-cycle current limit |
| Mode 001 Configuration | 2 full bridges or 4 half bridges; M3=0, M2=0, M1=1; OC latching shutdown |
| Mode 010 Configuration | 1 parallel full bridge; M3=0, M2=1, M1=0; cycle-by-cycle current limit |
| Mode 011 Configuration | 2 full bridges; M3=0, M2=1, M1=1; complementary PWM on second half bridge |
| Datasheet Status | request_only |
Product Overview
The DRV8412 is a Texas Instruments Power_Management Power_IC designed as a dual full-bridge PWM motor driver. Its output stage supports dual full-bridge operation or four half bridges, and the listed mode configurations also support one parallel full bridge and two full bridges with one PWM input per full bridge depending on M1, M2, and M3 logic settings.
The PVDD supply is specified for a 52 V maximum operating supply with 50 V nominal operation, and the recommended half-bridge PVDD_X range is 0 to 52.5 V. Recommended GVDD_X and VDD supplies are 10.8 V minimum, 12 V typical, and 13.2 V maximum. The recommended PWM switching frequency is up to 500 kHz, and the minimum PWM pulse duration is 50 ns for low-side on-time to charge the bootstrap capacitor.
The DRV8412 uses an HTSSOP (DDW), 44-pin, 14 mm x 8.1 mm package with an exposed power pad area of 34 mm2. Thermal data includes 24.5°C/W junction-to-ambient resistance, 0.2°C/W junction-to-case bottom resistance, and 5.0 W package power rating at TA = 25°C based on the EVM board layout.
Key Features
- Dual full-bridge or four half-bridge output configuration
- 52 V maximum operating PVDD supply voltage
- 2 x 3 A continuous current in dual full-bridge mode
- 2 x 6 A peak current in dual full-bridge mode
- 6 A continuous current in parallel bridge mode
- 12 A peak current in parallel bridge mode
- 500 kHz maximum recommended PWM switching frequency
- Up to 97% power-stage efficiency
- 110 mOhm MOSFET RDS(on) at TJ = 25°C
- Programmable cycle-by-cycle current limit using OC_ADJ resistor
- Undervoltage, overtemperature, overload, and short-circuit protection
- Open-drain active-low FAULT and OTW outputs
Typical Applications
- PWM motor drive stages
- Dual full-bridge motor control
- Four half-bridge motor control
- Parallel full-bridge motor drive
- High-current bridge drive channels
- Systems using cycle-by-cycle current limit
- Motor drivers requiring FAULT indication
- Motor drivers requiring OTW warning
Procurement Notes
When requesting a quote for DRV8412, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What output configurations does the DRV8412 support?
The DRV8412 supports dual full-bridge operation or four half bridges. Its mode table also lists one parallel full bridge and a two-full-bridge configuration using one PWM input per full bridge with complementary PWM on the second half bridge.
What supply voltages are recommended for DRV8412 operation?
The recommended PVDD_X range is 0 to 52.5 V, with 50 V listed as a nominal PVDD operating supply. GVDD_X and VDD are both recommended at 10.8 V minimum, 12 V typical, and 13.2 V maximum.
What current ratings apply in full-bridge and parallel modes?
In dual full-bridge mode, the DRV8412 supports 2 x 3 A continuous and 2 x 6 A peak output current. In parallel mode, it supports 6 A continuous current and 12 A peak current.
What protection and current-limit functions are included?
The device includes undervoltage, overtemperature, overload, and short-circuit protection. It also supports programmable cycle-by-cycle current limiting using an OC_ADJ resistor, with a 24 to 200 kOhm resistor range for cycle-by-cycle current-limit modes.
What package and thermal data are specified for DRV8412?
The DRV8412 is supplied in an HTSSOP (DDW), 44-pin, 14 mm x 8.1 mm package. Listed thermal data includes 24.5°C/W junction-to-ambient resistance, 0.2°C/W junction-to-case bottom resistance, and a 34 mm2 exposed power pad area.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.