Specifications
| Type | Description |
|---|---|
| Part Number | DRV8833 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Motor Supply Voltage Range | 2.7-10.8 V; Recommended operating condition, TA=25°C; source page 5 |
| Absolute Maximum Motor Supply Voltage | -0.3 to 11.8 V; Over operating free-air temperature range; source page 5 |
| Digital Input Pin Voltage Range | -0.3 to 5.75 V; Recommended operating condition, TA=25°C; source page 5 |
| Absolute Maximum Digital Input Pin Voltage | -0.5 to 7 V; Over operating free-air temperature range; source page 5 |
| Absolute Maximum xISEN Pin Voltage | -0.3 to 0.5 V; Over operating free-air temperature range; source page 5 |
| Continuous Output Current Per Bridge | 1.5 A RMS or DC; RTY package, VM=5 V, thermal limits observed; source page 5 |
| Output Current Per H-Bridge | 1.5 A RMS, 2 A peak; VM=5 V, 25°C, PWP and RTY package options; source page 1 |
| Output Current Per H-Bridge | 500 mA RMS, 2 A peak; VM=5 V, 25°C, PW package option; source page 1 |
| Parallel Output Current | 3 A RMS, 4 A peak; Outputs in parallel, PWP and RTY package options; source page 1 |
| Parallel Output Current | 1 A RMS, 4 A peak; Outputs in parallel, PW package option; source page 1 |
| Combined H-Bridge MOSFET On-Resistance | 360 mΩ; High-side plus low-side MOSFETs; source page 1 |
| Operating Junction Temperature | -40 to 150°C; Absolute maximum rating; source page 5 |
| Storage Temperature | -60 to 150°C; Absolute maximum rating; source page 5 |
| ESD Rating HBM | ±4000 V; Human body model, ANSI/ESDA/JEDEC JS-001, all pins; source page 5 |
| ESD Rating CDM | ±1500 V; Charged device model, JEDEC JESD22-C101, all pins; source page 5 |
| VM Operating Supply Current | 1.7 mA typ, 3 mA max; VM=5 V, xIN1=0 V, xIN2=0 V, TA=25°C; source page 6 |
| VM Sleep Mode Supply Current | 1.6 µA typ, 2.5 µA max; VM=5 V, TA=25°C; source page 6 |
| VM Undervoltage Lockout Voltage | 2.6 V typ; VM falling, TA=25°C; source page 6 |
| VM Undervoltage Lockout Hysteresis | 90 mV typ; TA=25°C; source page 6 |
| nSLEEP Input Low Voltage | 0.5 V max; TA=25°C; source page 6 |
| Input Low Voltage | 0.7 V max; All other logic pins, TA=25°C; source page 6 |
| nSLEEP Input High Voltage | 2.5 V min; TA=25°C; source page 6 |
| Input High Voltage | 2 V min; All other logic pins, TA=25°C; source page 6 |
| Input Hysteresis | 0.4 V typ; Logic-level inputs, TA=25°C; source page 6 |
| nSLEEP Input Pulldown Resistance | 500 kΩ typ; TA=25°C; source page 6 |
| Input Pulldown Resistance | 150 kΩ typ; All logic inputs except nSLEEP, TA=25°C; source page 6 |
| Input Low Current | 1 µA max; VIN=0 V, TA=25°C; source page 6 |
| nSLEEP Input High Current | 6.6 µA typ, 13 µA max; VIN=3.3 V, TA=25°C; source page 6 |
| Input High Current | 16.5 µA typ, 33 µA max; VIN=3.3 V, all logic inputs except nSLEEP, TA=25°C; source page 6 |
| Input Deglitch Time | 450 ns typ; Logic-level inputs, TA=25°C; source page 6 |
| nFAULT Output Low Voltage | 0.5 V max; IO=5 mA, open-drain output, TA=25°C; source page 6 |
| nFAULT Output High Leakage Current | 1 µA max; VO=3.3 V, open-drain output, TA=25°C; source page 6 |
| High-Side FET On-Resistance | 200 mΩ typ; VM=5 V, IO=500 mA, TJ=25°C; source page 6 |
| High-Side FET On-Resistance | 325 mΩ typ; VM=5 V, IO=500 mA, TJ=85°C; source page 6 |
| Low-Side FET On-Resistance | 160 mΩ typ; VM=5 V, IO=500 mA, TJ=25°C; source page 6 |
| Low-Side FET On-Resistance | 275 mΩ typ; VM=5 V, IO=500 mA, TJ=85°C; source page 6 |
| Off-State Leakage Current | -1 to 1 µA; VM=5 V, TJ=25°C, VOUT=0 V; source page 6 |
| Current Control PWM Frequency | 50 kHz typ; Internal PWM frequency; source page 6 |
| Output Rise Time | 180 ns typ; VM=5 V, 16 Ω to GND, 10% to 90% VM; source page 6 |
| Output Fall Time | 160 ns typ; VM=5 V, 16 Ω to GND, 10% to 90% VM; source page 6 |
| Propagation Delay INx to OUTx | 1.1 µs typ; VM=5 V; source page 6 |
| Dead Time | 450 ns typ; VM=5 V, internal dead time; source page 6 |
| Overcurrent Protection Trip Level | 2 A min, 3.3 A typ; Protection circuits, TA=25°C; source page 6 |
| Overcurrent Protection Deglitch Time | 4 µs typ; Protection circuits, TA=25°C; source page 6 |
| Overcurrent Protection Period | 1.35 ms typ; Protection circuits, TA=25°C; source page 6 |
| Thermal Shutdown Temperature | 150°C min, 160°C typ, 180°C max; Die temperature; source page 6 |
| Current Sense Trip Voltage | 160 mV min, 200 mV typ, 240 mV max; xISEN trip voltage, TA=25°C; source page 7 |
| Current Sense Blanking Time | 3.75 µs typ; Current control, TA=25°C; source page 7 |
| Start-Up Time | 1 ms typ; nSLEEP inactive high to H-bridge on; source page 7 |
| Recommended VM Bypass Capacitor | 10 µF minimum ceramic; Connect from VM to GND; source page 3 |
| Recommended VINT Bypass Capacitor | 2.2 µF, 6.3 V; Bypass VINT to GND; source page 3 |
| Recommended VCP Capacitor | 0.01 µF, 16 V minimum, X7R ceramic; Connect from VCP to VM; source page 3 |
| Datasheet Status | request_only |
Product Overview
The DRV8833 is a Texas Instruments dual H-bridge motor driver in the Power_Management category. It operates from a recommended 2.7-10.8 V motor supply and integrates high-side and low-side MOSFET output stages with 360 mΩ combined H-bridge on-resistance. The driver supports logic-level inputs, nSLEEP control, an open-drain nFAULT output, and internal timing such as 450 ns input deglitching and 450 ns dead time.
Output current capability is package dependent. PWP and RTY package options support 1.5 A RMS and 2 A peak per H-bridge at VM=5 V and 25°C, while the PW package option supports 500 mA RMS and 2 A peak. When outputs are paralleled, PWP and RTY options support 3 A RMS and 4 A peak, and the PW option supports 1 A RMS and 4 A peak.
Assembly options include TSSOP-16 5.00 mm x 4.40 mm, HTSSOP-16 5.00 mm x 4.40 mm, and WQFN-16 4.00 mm x 4.00 mm packages. The datasheet recommends a minimum 10 µF ceramic VM bypass capacitor, a 2.2 µF 6.3 V VINT bypass capacitor, and a 0.01 µF X7R ceramic VCP capacitor rated at 16 V minimum.
Key Features
- 2.7-10.8 V recommended motor supply range
- Dual H-bridge motor driver output structure
- 1.5 A RMS, 2 A peak per bridge on PWP and RTY
- 500 mA RMS, 2 A peak per bridge on PW
- 3 A RMS, 4 A peak with paralleled PWP and RTY outputs
- 360 mΩ combined high-side and low-side MOSFET resistance
- 1.6 µA typical VM sleep-mode supply current
- 50 kHz typical internal current-control PWM frequency
- Overcurrent protection with 3.3 A typical trip level
- Thermal shutdown at 160°C typical die temperature
- Open-drain nFAULT output with 0.5 V maximum low voltage
- Recommended VM, VINT, and VCP bypass capacitors specified
Typical Applications
- Dual H-bridge motor drive
- Low-voltage motor control
- Paralleled output motor drive
- Current-controlled motor outputs
- Sleep-mode motor systems
- Fault-monitored motor control
- Thermally protected motor drivers
Procurement Notes
When requesting a quote for DRV8833, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What motor supply range does the DRV8833 support?
The DRV8833 has a recommended motor supply voltage range of 2.7-10.8 V at TA=25°C. Its absolute maximum motor supply voltage rating is -0.3 to 11.8 V over the operating free-air temperature range.
How much output current is available per H-bridge?
Per H-bridge output current depends on package. PWP and RTY package options support 1.5 A RMS and 2 A peak at VM=5 V and 25°C. The PW package option supports 500 mA RMS and 2 A peak.
Can the DRV8833 outputs be connected in parallel?
The extracted datasheet facts specify parallel output ratings. With outputs in parallel, PWP and RTY package options support 3 A RMS and 4 A peak. The PW package option supports 1 A RMS and 4 A peak.
What protection functions are specified for the DRV8833?
The datasheet facts include undervoltage lockout at 2.6 V typical, overcurrent protection with a 3.3 A typical trip level, overcurrent deglitching and protection timing, and thermal shutdown at 160°C typical die temperature.
Which external capacitors are recommended around the DRV8833?
The datasheet recommends a 10 µF minimum ceramic capacitor from VM to GND, a 2.2 µF 6.3 V capacitor from VINT to GND, and a 0.01 µF X7R ceramic capacitor rated 16 V minimum from VCP to VM.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.