Specifications
| Type | Description |
|---|---|
| Part Number | HD3SS3220 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | VQFN RNH, 30 pins, 2.50 mm x 4.50 mm body |
| Integrated mux configuration | USB SuperSpeed 2:1 mux; integrated with DRP port controller |
| Supported USB data rate | Up to 10 Gbps; USB 3.1 Gen 1 and Gen 2 |
| Supported power delivery advertisement/detection | Up to 15 W, 3 A; USB Type-C current advertisement and detection |
| Port role modes | DFP, UFP, DRP; mode configuration options |
| Type-C current modes | Default, Mid, High; DFP advertisement and UFP detection |
| VCONN support | Supported for active cables |
| Audio accessory support | Supported on HD3SS3220; not supported on HD3SS3220L |
| Debug accessory support | HD3SS3220 supports UFP/DFP/DRP debug; HD3SS3220L supports debug accessory only as UFP |
| Try.SRC and Try.SNK support | Supported in DRP modes |
| Configuration control interfaces | GPIO and I2C for device configuration control |
| Operating temperature range | -40 to 85 °C; industrial temperature range |
| VDD5 absolute maximum voltage | -0.3 to 6 V; 5 V supply voltage |
| VCC33 absolute maximum voltage | -0.3 to 4 V; 3.3 V supply voltage |
| Control pin absolute maximum voltage | -0.3 to VDD5 + 0.3 V; ADDR, PORT, ID, INT_N/OUT3, ENn_CC, SDA/OUT1, SCL/OUT2 |
| CC pin absolute maximum voltage | -0.3 to 6 V; CC1, CC2 control pins |
| ENn_MUX and DIR absolute maximum voltage | -0.3 to VCC33 + 0.3 V; ENn_MUX, DIR pins |
| VBUS_DET absolute maximum voltage | -0.3 to 4 V; VBUS_DET pin |
| SuperSpeed pin absolute maximum voltage | -0.3 to 2.5 V; RX/TX p/n and RX/TX 1/2 p/n pins |
| Storage temperature | -65 to 150 °C; absolute maximum rating |
| HBM ESD rating | ±2000 V; ANSI/ESDA/JEDEC JS-001 |
| CDM ESD rating | ±1500 V; JEDEC JESD22-C101 |
| VDD5 recommended supply voltage | 4.5 to 5.5 V; VDD5 >= 5 V recommended with 200 mA VCONN current for VCONN >= 4.75 V at connector |
| VCC33 recommended supply voltage | 3 to 3.6 V; 3.3 V supply voltage range |
| I2C supply voltage range | 1.65 to 3.6 V; SDA and SCL pins |
| VDD5 supply ramp time | 25 ms max; recommended operating condition |
| High-speed differential voltage | 0 to 1.8 Vpp; high-speed signal pins |
| High-speed common-mode voltage | 0 to 2 V; high-speed signal pins |
| Operating ambient temperature, HD3SS3220 | 0 to 70 °C |
| Operating ambient temperature, HD3SS3220I | -40 to 85 °C |
| System VBUS input voltage | 4 to 28 V, 5 V nominal; through 900 kΩ resistor |
| VCONN bulk capacitance | 10 to 200 µF; only when VCONN is on, placed on VDD5 |
| External pull-up resistor on open-drain I/Os | 200 kΩ nominal; OUT1, OUT2, INT/OUT3, ID, VCONN_FAULT_N, DIR pins |
| Tri-level input external pull-up resistor | 4.7 kΩ nominal; PORT and ADDR pins |
| CURRENT_MODE resistor for 1.5 A advertisement | 500 kΩ nominal; external pull-up resistor on CURRENT_MODE pin |
| CURRENT_MODE resistor for 3 A advertisement | 10 kΩ nominal; external pull-up resistor on CURRENT_MODE pin |
| I2C bus external pull-up resistor | 2.2 kΩ nominal; could be 4.7 kΩ or higher |
| VBUS_DET external resistor | 880 to 910 kΩ, 900 kΩ nominal; external resistor on VBUS_DET pin |
| Junction-to-ambient thermal resistance | 60.9 °C/W; RNH VQFN, 30 pins |
| Junction-to-case top thermal resistance | 50.4 °C/W; RNH VQFN, 30 pins |
| Junction-to-board thermal resistance | 22.8 °C/W; RNH VQFN, 30 pins |
| Junction-to-top characterization parameter | 1.7 °C/W; RNH VQFN, 30 pins |
| Junction-to-board characterization parameter | 22.6 °C/W; RNH VQFN, 30 pins |
| Junction-to-case bottom thermal resistance | 12.1 °C/W; RNH VQFN, 30 pins |
| Active mode current consumption | 0.7 mA typ, 0.9 mA max; both CC controller and SS mux on, ENn_CC/MUX = L |
| CC-only active current consumption | 0.2 mA typ; CC controller on and SS mux off, ENn_CC = L, ENn_MUX = H |
| Shutdown current consumption | 5 µA max; ENn_CC/MUX = H |
| CC dead-battery pulldown resistance | 4.1 to 6.1 kΩ, 5.1 kΩ typ; pulldown resistor when in dead-battery mode |
| CC UFP/DRP pulldown resistance | 4.6 to 5.6 kΩ, 5.1 kΩ typ; pulldown resistor when in UFP or DRP mode |
| UFP CC attach detect voltage for default USB current | 0.25 to 0.61 V; configured as UFP, DFP advertising default USB current |
| CURRENT_MODE default setting | Low/default, 900 mA; CURRENT_MODE pin low, DFP or DFP in DRP mode while in GPIO mode |
| CURRENT_MODE medium setting | 1.5 A; install 500 kΩ to VDD5 on CURRENT_MODE pin |
| CURRENT_MODE high setting | 3 A; install 10 kΩ to VDD5 on CURRENT_MODE pin |
| PORT pin high mode | DFP; pull up PORT to VDD5 |
| PORT pin no-connect mode | DRP; leave PORT unconnected |
| PORT pin low mode | UFP; pull down or tie PORT to GND |
| ADDR high configuration | I2C enabled, 7-bit address 0x67; ADDR connected to VDD5 |
| ADDR no-connect configuration | GPIO mode; I2C disabled; ADDR pin NC |
| ADDR low configuration | I2C enabled, 7-bit address 0x47; ADDR connected to GND |
| Datasheet Status | request_only |
Product Overview
The HD3SS3220 is a Texas Instruments USB Type-C DRP port controller categorized under Signal_Chain. It combines a DRP port controller with an integrated USB SuperSpeed 2:1 mux, supporting USB 3.1 Gen 1 and Gen 2 signaling up to 10 Gbps. Port role configuration covers DFP, UFP, and DRP operation, with Try.SRC and Try.SNK support for DRP behavior.
Power and Type-C interface functions include Default, Mid, and High current modes, with current advertisement and detection up to 15 W and 3 A. The device supports VCONN for active cables, audio accessory detection on HD3SS3220, and debug accessory support across UFP, DFP, and DRP modes. Configuration is available through GPIO and I2C, with ADDR selecting either GPIO mode or I2C addresses 0x67 and 0x47.
The package is a 30-pin VQFN RNH with a 2.50 mm x 4.50 mm body. Recommended supplies include 4.5 to 5.5 V on VDD5 and 3 to 3.6 V on VCC33, with specified resistor values for VBUS_DET, CURRENT_MODE, I2C pullups, and tri-level inputs.
Key Features
- USB SuperSpeed 2:1 mux integrated with DRP controller
- Supports USB 3.1 Gen 1 and Gen 2 up to 10 Gbps
- Advertises and detects Type-C current up to 15 W, 3 A
- Configurable DFP, UFP, and DRP port role modes
- Default, Mid, and High Type-C current modes
- VCONN support for active USB Type-C cables
- Audio accessory support on HD3SS3220 device variant
- Debug accessory support across UFP, DFP, and DRP modes
- Try.SRC and Try.SNK support for DRP operation
- GPIO and I2C configuration control interfaces
Typical Applications
- USB Type-C DRP ports
- USB 3.1 Gen 1 routing
- USB 3.1 Gen 2 routing
- DFP and UFP port designs
- Active cable VCONN support
- Audio accessory detection ports
- Debug accessory detection ports
- GPIO configured Type-C systems
- I2C controlled Type-C systems
Procurement Notes
When requesting a quote for HD3SS3220, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the HD3SS3220?
The HD3SS3220 is a Texas Instruments USB Type-C DRP port controller in the Signal_Chain category. It integrates a USB SuperSpeed 2:1 mux with DRP controller functions for DFP, UFP, and DRP Type-C port role operation.
What USB data rate does HD3SS3220 support?
The HD3SS3220 supports USB 3.1 Gen 1 and Gen 2 operation with data rates up to 10 Gbps. The extracted datasheet facts identify the integrated mux as a USB SuperSpeed 2:1 mux.
How is the HD3SS3220 configured for port role and control?
The PORT pin selects DFP, DRP, or UFP mode using pullup, no-connect, or pulldown conditions. Device configuration control is available through GPIO and I2C, with ADDR selecting GPIO mode or I2C addresses 0x67 and 0x47.
What package is used for the HD3SS3220?
The HD3SS3220 uses the RNH VQFN package with 30 pins and a 2.50 mm x 4.50 mm body. Thermal parameters include 60.9 °C/W junction-to-ambient resistance and 12.1 °C/W junction-to-case bottom resistance.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.