Specifications
| Type | Description |
|---|---|
| Part Number | HD3SS3212 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 20-pin VQFN RKS, 2.50 mm x 4.50 mm nominal body, 0.5-mm pitch |
| Function | Two-channel differential 2:1/1:2 mux/demux passive switch; USB Type-C ecosystem, USB 3.1 Gen 1 and Gen 2 data rates |
| Maximum Data Rate | 10 Gbps; high-speed differential operation |
| Supported Interfaces | USB 3.1, MIPI DSI/CSI, FPD-Link III, LVDS, PCIe Gen II/III; compatible high-speed interface applications |
| Supply Voltage | 3.3 V nominal; single supply voltage VCC |
| Recommended Supply Voltage | 2.7-3.6 V; over operating free-air temperature range |
| Absolute Maximum Supply Voltage | -0.5 to 4 V; VCC, stress rating only |
| Absolute Maximum Differential I/O Voltage | -0.5 to 2.5 V; differential I/O pins, stress rating only |
| Absolute Maximum Control Pin Voltage | -0.5 to VCC + 0.5 V; control pins, stress rating only |
| Storage Temperature | -65 to 150 °C; Tstg |
| HBM ESD Rating | ±2000 V; human-body model, ANSI/ESDA/JEDEC JS-001 |
| CDM ESD Rating | ±500 V; charged-device model, JEDEC JESD22-C101 |
| Input High Voltage | 1.7 V to VCC; SEL and OEn pins |
| Input Low Voltage | -0.1 to 0.8 V; SEL and OEn pins |
| High-Speed Differential Signal Voltage | 0 to 1.8 Vpp; high-speed signal pins |
| High-Speed Common-Mode Voltage | 0 to 2 V; high-speed signal pins |
| Commercial Operating Temperature | 0 to 70 °C; HD3SS3212RKS |
| Industrial Operating Temperature | -40 to 85 °C; HD3SS3212IRKS |
| Active Current | 0.6 mA typ, 0.8 mA max; VCC = 3.3 V, OEn = 0 |
| Shutdown Current | 5 µA typ, 20 µA max; VCC = 3.3 V, OEn = VCC |
| Operational Power Consumption | <2 mW; operational mode |
| Shutdown Power Consumption | <20 µW; shutdown mode by OEn pin |
| Output ON Capacitance | 0.6 pF typ; CON |
| Output OFF Capacitance | 0.8 pF typ; COFF |
| Output ON Resistance | 5 Ω typ, 8 Ω max; VCC = 3.3 V, VCM = 0 to 2 V, IO = -8 mA |
| ON Resistance Match | 0.5 Ω typ; between pairs of same channel, VCC = 3.3 V, -0.35 V ≤ VIN ≤ 2.35 V, IO = -8 mA |
| ON Resistance Flatness | 1 Ω typ; RON(max) - RON(min), VCC = 3.3 V, -0.35 V ≤ VIN ≤ 2.35 V |
| Control Pin Input High Current | 1 µA max; SEL and OEn pins |
| Control Pin Input Low Current | 1 µA max; SEL and OEn pins |
| Selected High-Speed Pin Input High Current | 1 µA max; VIN = 2 V for selected port, A and B with SEL = 0, and A and C with SEL = VCC |
| Non-Selected High-Speed Pin Input High Current | 100 µA typ, 140 µA max; VIN = 2 V for non-selected port, C with SEL = 0, and B with SEL = VCC; 20-kΩ pulldown in non-selected port |
| High-Speed Pin Input Low Current | 1 µA max; high-speed pins Ax/Bx/Cx p/n |
| 3-dB Bandwidth | 8 GHz; differential high-speed path |
| Differential Insertion Loss | -1.6 dB typ; f = 5 GHz |
| Differential Return Loss | -12 dB typ; f = 5 GHz |
| Differential OFF Isolation | -19 dB typ; f = 5 GHz |
| Differential Crosstalk | -32 dB typ; f = 5 GHz |
| Switch Propagation Delay | 80 ps typ; see Figure 3 |
| SEL-to-Switch ON Time | 0.5 µs typ; see Figure 2 |
| SEL-to-Switch OFF Time | 0.5 µs typ; see Figure 2 |
| Intra-Pair Output Skew | 6 ps typ; see Figure 3 |
| Inter-Pair Output Skew | 20 ps typ; see Figure 3 |
| OEn Logic Function | Low = normal operation, High = shutdown; active-low chip enable pin |
| SEL Logic Function | Low = Port A to Port B, High = Port A to Port C; port select pin |
| High-Speed Port Pulldown | 20 kΩ; pulldown resistors switched in when a port is not selected and switched out when selected |
| Junction-to-Ambient Thermal Resistance | 46.6 °C/W; RKS VQFN, 20 pins |
| Junction-to-Case Top Thermal Resistance | 41.8 °C/W; RKS VQFN, 20 pins |
| Junction-to-Board Thermal Resistance | 4.4 °C/W; RKS VQFN, 20 pins |
| Junction-to-Top Characterization Parameter | 17.6 °C/W; RKS VQFN, 20 pins |
| Junction-to-Board Characterization Parameter | 1.6 °C/W; RKS VQFN, 20 pins |
| Junction-to-Case Bottom Thermal Resistance | 17.6 °C/W; RKS VQFN, 20 pins |
| Datasheet Status | request_only |
Product Overview
The HD3SS3212 is a Texas Instruments USB 3.1 differential mux demux for Signal_Chain designs. It is defined as a two-channel differential 2:1/1:2 passive switch for USB Type-C ecosystem use, including USB 3.1 Gen 1 and Gen 2 data rates. The high-speed differential path supports up to 10 Gbps and has an 8 GHz typical 3-dB bandwidth.
The device operates from a 3.3 V nominal VCC supply, with a recommended supply range of 2.7 V to 3.6 V across the operating free-air temperature range. Active current is 0.6 mA typical and 0.8 mA maximum at VCC = 3.3 V with OEn = 0. Shutdown current is 5 µA typical and 20 µA maximum with OEn = VCC.
HD3SS3212 uses a 20-pin VQFN RKS package with a 2.50 mm x 4.50 mm nominal body and 0.5-mm pitch. Logic control is provided by OEn and SEL: OEn low enables normal operation, OEn high selects shutdown, SEL low connects Port A to Port B, and SEL high connects Port A to Port C. Supported interface applications include USB 3.1, MIPI DSI/CSI, FPD-Link III, LVDS, and PCIe Gen II/III.
Key Features
- Two-channel differential 2:1/1:2 passive mux/demux switch
- Supports USB 3.1 Gen 1 and Gen 2 data rates
- 10 Gbps maximum high-speed differential data rate
- Compatible with USB 3.1, MIPI, FPD-Link III, LVDS, PCIe
- 3.3 V nominal single-supply VCC operation
- 2.7 V to 3.6 V recommended supply range
- 8 GHz typical 3-dB differential bandwidth
- 5 Ω typical ON resistance at 3.3 V
- OEn pin selects normal operation or shutdown
- SEL pin routes Port A to Port B or C
Typical Applications
- USB Type-C ecosystems
- USB 3.1 switching paths
- MIPI DSI and CSI routing
- FPD-Link III differential links
- LVDS signal switching
- PCIe Gen II/III muxing
- High-speed differential interface selection
Procurement Notes
When requesting a quote for HD3SS3212, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What function does the HD3SS3212 provide?
The HD3SS3212 provides a two-channel differential 2:1/1:2 passive mux/demux switch function for USB Type-C ecosystem designs, including USB 3.1 Gen 1 and Gen 2 data-rate applications.
What data rate does the HD3SS3212 support?
The HD3SS3212 supports high-speed differential operation up to 10 Gbps. Its differential high-speed path has an 8 GHz typical 3-dB bandwidth, with typical insertion loss of -1.6 dB at 5 GHz.
How are the HD3SS3212 ports controlled?
The OEn pin is an active-low chip enable: low selects normal operation and high selects shutdown. The SEL pin selects the routing path, with low connecting Port A to Port B and high connecting Port A to Port C.
What package is used for the HD3SS3212?
The HD3SS3212 is specified in a 20-pin VQFN RKS package. The package has a 2.50 mm x 4.50 mm nominal body and a 0.5-mm pitch.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.