Specifications
| Type | Description |
|---|---|
| Part Number | NE5532DR |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | SOIC-8 4.90 mm x 3.91 mm; PDIP-8 9.81 mm x 6.35 mm; SO-8 6.20 mm x 5.30 mm |
| Number of amplifiers | 2; Dual operational amplifier |
| Equivalent input noise voltage | 5 nV/√Hz typ; f = 1 kHz |
| Unity-gain bandwidth | 12 MHz typ; VCC± = ±15 V, TA = 25°C |
| Common-mode rejection ratio | 70 dB min, 100 dB typ; VIC = VICR min, VCC± = ±15 V, TA = 25°C |
| Large-signal differential-voltage amplification | 15 V/mV min, 50 V/mV typ; RL ≥ 600 Ω, VO = ±10 V, TA = 25°C |
| Large-signal differential-voltage amplification | 10 V/mV min; RL ≥ 600 Ω, VO = ±10 V, full temperature range |
| Large-signal differential-voltage amplification | 25 V/mV min, 100 V/mV typ; RL ≥ 2 kΩ, VO = ±10 V, TA = 25°C |
| Large-signal differential-voltage amplification | 15 V/mV min; RL ≥ 2 kΩ, VO = ±10 V, full temperature range |
| Slew rate | 5 V/µs typ; Unity gain, VCC± = ±15 V, TA = 25°C |
| Input offset voltage | 0.5 mV typ, 4 mV max; VO = 0, TA = 25°C, VCC± = ±15 V |
| Input offset voltage | 5 mV max; VO = 0, full temperature range, VCC± = ±15 V |
| Input offset current | 10 nA typ, 150 nA max; TA = 25°C, VCC± = ±15 V |
| Input offset current | 200 nA max; Full temperature range, VCC± = ±15 V |
| Input bias current | 200 nA typ, 800 nA max; TA = 25°C, VCC± = ±15 V |
| Input bias current | 1000 nA max; Full temperature range, VCC± = ±15 V |
| Common-mode input-voltage range | ±12 V min, ±13 V typ; VCC± = ±15 V, TA = 25°C |
| Input resistance | 30 kΩ min, 300 kΩ typ; VCC± = ±15 V, TA = 25°C |
| Supply-voltage rejection ratio | 80 dB min, 100 dB typ; VCC± = ±9 V to ±15 V, VO = 0 |
| Output short-circuit current | 38 mA typ; VCC± = ±15 V, TA = 25°C |
| Total supply current | 6 mA typ, 16 mA max; VO = 0, no load, VCC± = ±15 V, TA = 25°C |
| Equivalent input noise voltage | 8 nV/√Hz typ; f = 30 Hz, VCC± = ±15 V, TA = 25°C |
| Equivalent input noise voltage | 5 nV/√Hz typ; f = 1 kHz, VCC± = ±15 V, TA = 25°C |
| Equivalent input noise current | 2.7 pA/√Hz typ; f = 30 Hz, VCC± = ±15 V, TA = 25°C |
| Equivalent input noise current | 0.7 pA/√Hz typ; f = 1 kHz, VCC± = ±15 V, TA = 25°C |
| Recommended positive supply voltage | 5 V min, 15 V max; Recommended operating conditions |
| Recommended negative supply voltage | -5 V min, -15 V max; Recommended operating conditions |
| Operating free-air temperature | 0°C to 70°C; NE5532, NE5532A |
| Operating free-air temperature | -40°C to 85°C; SA5532, SA5532A |
| Absolute maximum positive supply voltage | 0 V to +18 V; Over operating free-air temperature range |
| Absolute maximum negative supply voltage | -18 V to 0 V; Over operating free-air temperature range |
| Absolute maximum input voltage | -15 V to +15 V; Either input; magnitude must not exceed supply voltage magnitude |
| Absolute maximum input current | -10 mA to +10 mA; Over operating free-air temperature range |
| Output short-circuit duration | Unlimited; Short to ground or either supply; limited by maximum dissipation rating |
| Operating virtual-junction temperature | +150°C max; Absolute maximum rating |
| Storage temperature range | -60°C to +125°C; Absolute maximum rating |
| ESD rating, HBM | 1000 V; ANSI/ESDA/JEDEC JS-001, all pins |
| ESD rating, CDM | 1000 V; JEDEC JESD22-C101, all pins |
| Junction-to-ambient thermal resistance | 97°C/W; D package, 8 pins, JESD 51-7 |
| Junction-to-ambient thermal resistance | 85°C/W; P package, 8 pins, JESD 51-7 |
| Junction-to-ambient thermal resistance | 95°C/W; PS package, 8 pins, JESD 51-7 |
| Pin 1 function | OUT1; Output, 8-pin SOIC/PDIP/SO top view |
| Pin 2 function | 1IN-; Inverting input, 8-pin SOIC/PDIP/SO top view |
| Pin 3 function | 1IN+; Noninverting input, 8-pin SOIC/PDIP/SO top view |
| Pin 4 function | VCC-; Negative supply, 8-pin SOIC/PDIP/SO top view |
| Pin 5 function | 2IN+; Noninverting input, 8-pin SOIC/PDIP/SO top view |
| Pin 6 function | 2IN-; Inverting input, 8-pin SOIC/PDIP/SO top view |
| Pin 7 function | 2OUT; Output, 8-pin SOIC/PDIP/SO top view |
| Pin 8 function | VCC+; Positive supply, 8-pin SOIC/PDIP/SO top view |
| Datasheet Status | request_only |
Product Overview
NE5532DR is a Texas Instruments dual low-noise operational amplifier in the Signal_Chain category. It contains two amplifier channels and is characterized for low input noise, including 5 nV/√Hz typical equivalent input noise voltage at 1 kHz and 8 nV/√Hz typical at 30 Hz under ±15 V operation at 25°C.
The amplifier is specified with 12 MHz typical unity-gain bandwidth and 5 V/µs typical slew rate at ±15 V and 25°C. DC parameters include 0.5 mV typical input offset voltage, 200 nA typical input bias current, and 10 nA typical input offset current at 25°C. Common-mode rejection is specified at 70 dB minimum and 100 dB typical.
Package options listed for this device family include SOIC-8, PDIP-8, and SO-8 outlines. The 8-pin top-view pinout assigns OUT1, 1IN-, 1IN+, VCC-, 2IN+, 2IN-, 2OUT, and VCC+ across pins 1 through 8, supporting two independent operational amplifier channels in one package.
Key Features
- Dual operational amplifier with two amplifier channels
- 5 nV/√Hz typical input noise voltage at 1 kHz
- 12 MHz typical unity-gain bandwidth at ±15 V
- 5 V/µs typical slew rate in unity gain
- 70 dB minimum common-mode rejection ratio
- 80 dB minimum supply-voltage rejection ratio
- 0.5 mV typical input offset voltage at 25°C
- 38 mA typical output short-circuit current
- SOIC-8, PDIP-8, and SO-8 package options
- 1000 V HBM and 1000 V CDM ESD ratings
Typical Applications
- Low-noise signal amplification
- Dual operational amplifier stages
- ±15 V analog signal chains
- Unity-gain amplifier configurations
- Common-mode signal rejection circuits
- Signal paths requiring 12 MHz bandwidth
- SOIC-8 or PDIP-8 assemblies
Procurement Notes
When requesting a quote for NE5532DR, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
How many amplifiers are integrated in the NE5532DR?
The NE5532DR is specified as a dual operational amplifier, with two amplifier channels in the device. The 8-pin pinout provides separate inputs and outputs for channel 1 and channel 2.
What input noise voltage is specified for NE5532DR?
The extracted datasheet facts list 5 nV/√Hz typical equivalent input noise voltage at 1 kHz. They also list 8 nV/√Hz typical equivalent input noise voltage at 30 Hz under ±15 V operation at 25°C.
What supply voltages are recommended for this operational amplifier?
Recommended operating conditions list a positive supply voltage from 5 V to 15 V and a negative supply voltage from -5 V to -15 V. Several electrical characteristics are specified at VCC± = ±15 V.
Which functions are assigned to pins 1 through 8?
The 8-pin top-view pinout assigns OUT1, 1IN-, 1IN+, VCC-, 2IN+, 2IN-, 2OUT, and VCC+ to pins 1 through 8 respectively for SOIC, PDIP, and SO packages.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.