Specifications
| Type | Description |
|---|---|
| Part Number | OP07CDR |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | D (SOIC, 8), 4.90 mm × 3.91 mm body size |
| Supply voltage absolute maximum, single supply | 44 V max; absolute maximum rating, over operating free-air temperature range |
| Supply voltage absolute maximum, dual supply | ±22 V max; absolute maximum rating, over operating free-air temperature range |
| Differential input voltage absolute maximum | ±30 V max; IN+ with respect to IN− |
| Single-ended input voltage absolute maximum | ±22 V max; magnitude must never exceed supply voltage magnitude or 15 V, whichever is less |
| Output short-circuit rating | Continuous; output shorted to ground or negative power supply; fast ramping shorts to positive supply can damage device |
| Operating junction temperature | -55°C to 150°C; absolute maximum rating |
| Storage temperature | -65°C to 150°C; absolute maximum rating |
| ESD rating, HBM | ±1000 V; human-body model, ANSI/ESDA/JEDEC JS-001 |
| ESD rating, CDM | ±1000 V; charged-device model, JEDEC JESD22-C101 |
| Recommended supply voltage, single supply | 6 V min, 36 V max; recommended operating conditions |
| Recommended supply voltage, dual supply | ±3 V min, ±18 V max; recommended operating conditions |
| Common-mode input voltage range | -13 V min, 13 V max; VS = ±15 V |
| Operating ambient temperature | 0°C to 70°C; recommended operating conditions |
| Junction-to-ambient thermal resistance | 127.6°C/W; D package, SOIC-8 |
| Junction-to-case top thermal resistance | 67.1°C/W; D package, SOIC-8 |
| Junction-to-board thermal resistance | 71.4°C/W; D package, SOIC-8 |
| Junction-to-top characterization parameter | 18.7°C/W; D package, SOIC-8 |
| Junction-to-board characterization parameter | 70.6°C/W; D package, SOIC-8 |
| Input offset voltage, OP07C | ±60 µV typ, ±85 µV max; TA = 25°C; max over TA = 0°C to 70°C, VS = ±15 V, RL = 2 kΩ to mid-supply, VCM = VOUT = mid-supply |
| Input offset voltage, OP07D | ±150 µV typ, ±250 µV max; TA = 25°C; max over TA = 0°C to 70°C, VS = ±15 V, RL = 2 kΩ to mid-supply, VCM = VOUT = mid-supply |
| Input offset voltage drift, OP07C | ±0.5 µV/°C typ; TA = 0°C to 70°C |
| Input offset voltage drift, OP07D | ±2.5 µV/°C typ; TA = 0°C to 70°C |
| Long-term drift of input offset voltage | ±0.4 µV/month typ; engineering estimate after first 30 days of operation |
| Offset adjustment range | ±4 mV typ; RS = 20 kΩ |
| Power supply rejection ratio | 7 µV/V typ, 32 µV/V max; 10 µV/V typ, 51 µV/V max over temperature; VS = ±3 V to ±18 V |
| Input bias current, OP07C | ±1.8 nA typ, ±2.2 nA max; TA = 0°C to 70°C, VS = ±15 V |
| Input bias current, OP07D | ±12 nA typ, ±14 nA max; TA = 0°C to 70°C, VS = ±15 V |
| Input bias current drift, OP07C | ±18 pA/°C typ |
| Input bias current drift, OP07D | ±50 pA/°C typ |
| Input offset current, OP07C | ±0.8 nA typ, ±1.6 nA max; TA = 0°C to 70°C, VS = ±15 V |
| Input offset current, OP07D | ±6 nA typ, ±8 nA max; TA = 0°C to 70°C, VS = ±15 V |
| Input offset current drift, OP07C | 12 pA/°C typ |
| Input offset current drift, OP07D | ±50 pA/°C typ |
| Input voltage noise | 0.38 µVPP typ; f = 0.1 Hz to 10 Hz |
| Input voltage noise density at 10 Hz | 10.5 nV/√Hz typ |
| Input voltage noise density at 100 Hz | 10.2 nV/√Hz typ |
| Input voltage noise density at 1 kHz | 9.8 nV/√Hz typ |
| Input current noise | 15 pApp typ; f = 0.1 Hz to 10 Hz |
| Input current noise density at 10 Hz | 0.35 pA/√Hz typ |
| Input current noise density at 100 Hz | 0.15 pA/√Hz typ |
| Input current noise density at 1 kHz | 0.13 pA/√Hz typ |
| Common-mode voltage | ±13 V min, ±14 V typ; ±13 V min, ±13.5 V typ over temperature; VS = ±15 V |
| Common-mode rejection ratio, OP07C | 100 dB min, 120 dB typ; 97 dB min, 120 dB typ over temperature; VCM = ±13 V |
| Common-mode rejection ratio, OP07D | 94 dB min, 110 dB typ; 94 dB min, 106 dB typ over temperature; VCM = ±13 V |
| Input resistance | 7 MΩ min, 33 MΩ typ; VS = ±15 V, TA = 25°C |
| Open-loop voltage gain, OP07C | 100 V/mV min, 400 V/mV typ; 1.4 V < VO < 11.4 V, RL = 500 kΩ |
| Open-loop voltage gain, OP07D | 400 V/mV typ; 1.4 V < VO < 11.4 V, RL = 500 kΩ |
| Open-loop voltage gain at VO = ±10 V | 120 V/mV min, 400 V/mV typ |
| Open-loop voltage gain over temperature | 100 V/mV min, 400 V/mV typ; VO = ±10 V, TA = -40°C to +125°C |
| Unity gain bandwidth | 0.4 MHz min, 0.6 MHz typ; VS = ±15 V, TA = 25°C |
| Slew rate | 0.3 V/µs typ; VS = 5 V, RL = 2 kΩ |
| Voltage output swing, RL = 2 kΩ | ±11.5 V min, ±12.8 V typ; ±11 V min, ±12.6 V typ over temperature; VS = ±15 V |
| Voltage output swing, RL = 10 kΩ | ±12 V min, ±13 V typ; VS = ±15 V |
| Voltage output swing, RL = 1 kΩ | ±12 V typ; VS = ±15 V |
| Power dissipation at ±15 V | 80 mW typ, 150 mW max; no load |
| Power dissipation at ±3 V | 4 mW typ, 8 mW max; no load |
| Pin 1 function | OFFSET N1; external input offset voltage adjustment |
| Pin 2 function | IN−; inverting input |
| Pin 3 function | IN+; noninverting input |
| Pin 4 function | V−; negative supply |
| Pin 5 function | NC; do not connect |
| Pin 6 function | OUT; output |
| Pin 7 function | V+; positive supply |
| Pin 8 function | OFFSET N2; external input offset voltage adjustment |
| Datasheet Status | request_only |
Product Overview
OP07CDR is a Texas Instruments precision operational amplifier for Signal_Chain applications requiring controlled offset, bias, noise, and gain behavior. In the D SOIC-8 package, it uses an 8-pin layout with inverting and noninverting inputs, positive and negative supplies, output, no-connect pin, and two offset-adjust pins for external input offset voltage adjustment.
Key Features
- Precision operational amplifier in D SOIC-8 package
- 6 V to 36 V recommended single-supply operation
- ±3 V to ±18 V recommended dual-supply operation
- ±60 µV typical OP07C input offset voltage
- 0.4 MHz minimum, 0.6 MHz typical unity gain bandwidth
- 0.3 V/µs typical slew rate at 5 V supply
- 0.38 µVPP typical input voltage noise from 0.1 Hz to 10 Hz
- 100 dB minimum OP07C common-mode rejection ratio
- Continuous output short-circuit rating to ground or negative supply
- Offset adjustment pins support external input offset trimming
Typical Applications
- Precision signal conditioning
- Low-offset analog amplification
- Sensor interface amplifiers
- Calibrated measurement circuits
- Low-frequency noise-sensitive signal paths
- Dual-supply analog front ends
- Offset-trimmed amplifier stages
Procurement Notes
When requesting a quote for OP07CDR, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What supply range is recommended for OP07CDR operation?
The extracted operating conditions list 6 V to 36 V for single-supply operation and ±3 V to ±18 V for dual-supply operation. Absolute maximum ratings are higher, but circuit operation should follow the recommended operating conditions.
What package is used for the OP07CDR device?
OP07CDR is specified in the D package, an SOIC-8 package with a 4.90 mm × 3.91 mm body size. The thermal data includes 127.6°C/W junction-to-ambient resistance for this D SOIC-8 package.
What offset performance is listed for this precision amplifier?
For OP07C conditions, input offset voltage is ±60 µV typical and ±85 µV maximum. For OP07D conditions, the listed input offset voltage is ±150 µV typical and ±250 µV maximum under the stated ±15 V test setup.
Does OP07CDR include offset adjustment pins?
Yes. Pin 1 is OFFSET N1 and pin 8 is OFFSET N2. Both are identified for external input offset voltage adjustment, with an offset adjustment range of ±4 mV typical when RS is 20 kΩ.
What noise values are specified for OP07CDR?
The extracted data lists 0.38 µVPP typical input voltage noise from 0.1 Hz to 10 Hz. Voltage noise density is 10.5 nV/√Hz at 10 Hz, 10.2 nV/√Hz at 100 Hz, and 9.8 nV/√Hz at 1 kHz.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.