Specifications
| Type | Description |
|---|---|
| Part Number | PCM5142 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 28-pin TSSOP, body size 9.70 mm x 4.40 mm |
| DAC Architecture | Advanced segment-DAC architecture |
| Audio Output Type | Ground-centered single-ended outputs; 2.1 V RMS outputs; DC-blocking capacitors not required |
| Integrated Processing | Programmable miniDSP core supporting filters, dynamic range controls, custom interpolators, and other processing |
| Audio Interface Resolution | 16, 20, 24, and 32 bit |
| PCM Data Formats | I2S, left-justified, right-justified, TDM/DSP |
| Control Interfaces | SPI or I2C |
| Configuration Modes | Software or hardware configuration |
| Clocking Feature | Integrated audio PLL with BCK reference; generates SCK internally; supports 3-wire I2S connection |
| Dynamic Range | 112 dB |
| SNR | 112 dB |
| THD | -93 dB |
| Typical SNR | 112 dB at 3.3-V power supply |
| Typical Dynamic Range | 112 dB at 3.3-V power supply |
| THD+N | -93 dB at -1 dBFS, 3.3-V power supply |
| Full-Scale Single-Ended Output | 2.1 V RMS, ground-centered output, 3.3-V power supply |
| Normal Digital Filter Latency | 20 tS with 8x oversampling digital filter |
| Low-Latency Digital Filter Latency | 3.5 tS with 8x oversampling digital filter |
| Sampling Frequency Range | 8 kHz to 384 kHz |
| System Clock Frequency | Up to 50 MHz; 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072 fS multiples |
| Hardwired Gain Setting | 0 dB when ATT2:ATT1:ATT0 = 000 |
| Hardwired Gain Setting | 3 dB when ATT2:ATT1:ATT0 = 001 |
| Hardwired Gain Setting | 6 dB when ATT2:ATT1:ATT0 = 010 |
| Hardwired Gain Setting | 9 dB when ATT2:ATT1:ATT0 = 011 |
| Hardwired Gain Setting | 12 dB when ATT2:ATT1:ATT0 = 100 |
| Hardwired Gain Setting | 15 dB when ATT2:ATT1:ATT0 = 101 |
| Hardwired Attenuation Setting | -6 dB when ATT2:ATT1:ATT0 = 110 |
| Hardwired Attenuation Setting | -3 dB when ATT2:ATT1:ATT0 = 111 |
| Charge Pump Supply Pin | 3.3 V CPVDD pin function |
| Negative Charge Pump Rail | -3.3 V VNEG terminal for decoupling |
| Analog Supply Pin | 3.3 V AVDD pin function |
| Internal Logic Supply Rail | 1.8 V LDOO terminal for decoupling |
| Digital Supply Voltage Pin | 3.3 V or 1.8 V DVDD pin function |
| Analog Gain Selector | 0 dB / -6 dB; AGNS low = 2 V RMS output, high = 1 V RMS output |
| Filter Select Control | Normal latency / low latency; FLT low = normal latency, high = low latency |
| Audio Format Selection | I2S / left-justified; FMT low = I2S, high = left-justified |
| Soft Mute Control | Low = soft mute, high = soft un-mute on XSMT pin |
| Absolute Maximum Supply Voltage | -0.3 V to 3.9 V for AVDD, CPVDD, DVDD over operating free-air temperature range |
| Absolute Maximum LDO Voltage | -0.3 V to 2.25 V with DVDD at 1.8 V |
| Absolute Maximum Digital Input Voltage | -0.3 V to 2.25 V with DVDD at 1.8 V |
| Absolute Maximum Digital Input Voltage | -0.3 V to 3.9 V with DVDD at 3.3 V |
| Absolute Maximum Analog Input Voltage | -0.3 V to 3.9 V over operating free-air temperature range |
| Operating Junction Temperature | -40 °C to 130 °C |
| Storage Temperature | -65 °C to 150 °C |
| ESD Rating | ±2000 V human-body model, ANSI/ESDA/JEDEC JS-001 |
| ESD Rating | ±750 V charged-device model, JEDEC JESD22-C101 |
| Recommended Analog Supply Voltage | 3.0 V min, 3.3 V nom, 3.46 V max in VCOM mode, referenced to AGND |
| Recommended Analog Supply Voltage | 3.2 V min, 3.3 V nom, 3.46 V max in VREF mode, referenced to AGND |
| Recommended Digital Supply Voltage | 1.65 V min, 1.8 V nom, 1.95 V max for DVDD 1.8-V operation, referenced to DGND |
| Recommended Digital Supply Voltage | 3.1 V min, 3.3 V nom, 3.46 V max for DVDD 3.3-V operation, referenced to DGND |
| Recommended Charge Pump Supply Voltage | 3.1 V min, 3.3 V nom, 3.46 V max for CPVDD referenced to CPGND |
| Master Clock Frequency | 50 MHz max |
| Stereo Line Output Load Resistance | 1 kΩ min, 10 kΩ max for LOL and LOR |
| Datasheet Status | request_only |
Product Overview
The PCM5142 is a Texas Instruments stereo audio DAC for Signal_Chain designs. It is supplied in a 28-pin TSSOP package with a 9.70 mm x 4.40 mm body size and uses an advanced segment-DAC architecture. The audio outputs are ground-centered, single-ended outputs, supporting 2.1 V RMS full-scale output from a 3.3-V power supply without requiring DC-blocking capacitors.
Digital audio support includes 16-, 20-, 24-, and 32-bit word lengths with I2S, left-justified, right-justified, and TDM/DSP PCM formats. The integrated audio PLL can use BCK as a reference to generate SCK internally, supporting a 3-wire I2S connection. Control is available through SPI or I2C, with software or hardware configuration modes.
The device includes a programmable miniDSP core for filters, dynamic range controls, custom interpolators, and other processing. Typical performance includes 112 dB SNR, 112 dB dynamic range, -93 dB THD, and -93 dB THD+N at -1 dBFS with a 3.3-V supply. It supports 8 kHz to 384 kHz sampling and normal or low-latency digital filter operation.
Key Features
- Advanced segment-DAC architecture for stereo audio conversion
- Ground-centered single-ended outputs with 2.1 V RMS level
- 112 dB SNR and 112 dB dynamic range
- -93 dB THD and -93 dB THD+N performance
- Programmable miniDSP core for audio processing functions
- Supports 16, 20, 24, and 32 bit audio words
- I2S, left-justified, right-justified, and TDM/DSP formats
- SPI or I2C control with software or hardware configuration
- Integrated audio PLL supports BCK-referenced 3-wire I2S operation
- Normal and low-latency 8x oversampling digital filter modes
- 8 kHz to 384 kHz sampling frequency range
- 28-pin TSSOP package with 9.70 mm x 4.40 mm body
Typical Applications
- Stereo audio DAC stages
- Ground-centered line output circuits
- I2S audio interface designs
- TDM/DSP audio data systems
- SPI-controlled audio signal chains
- I2C-controlled audio signal chains
- Low-latency digital audio playback
- miniDSP-based audio processing
Procurement Notes
When requesting a quote for PCM5142, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the PCM5142?
The PCM5142 is a Texas Instruments stereo audio DAC in the Signal_Chain category. It uses an advanced segment-DAC architecture and provides ground-centered single-ended analog audio outputs from a 28-pin TSSOP package.
Which audio data formats does PCM5142 support?
The PCM5142 supports I2S, left-justified, right-justified, and TDM/DSP PCM audio data formats. Accepted audio word lengths are 16, 20, 24, and 32 bit.
What are the main audio performance ratings?
The PCM5142 has 112 dB SNR and 112 dB dynamic range. The listed THD is -93 dB, and THD+N is -93 dB at -1 dBFS with a 3.3-V power supply.
Does PCM5142 require DC-blocking capacitors on the outputs?
The extracted datasheet facts describe ground-centered single-ended outputs with 2.1 V RMS output and state that DC-blocking capacitors are not required for those outputs.
How can the PCM5142 be controlled or configured?
The PCM5142 supports SPI or I2C control interfaces and can be configured through software or hardware configuration modes. Hardware pins also support gain, filter, format, analog gain, and soft mute control functions.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.