Specifications
| Type | Description |
|---|---|
| Part Number | DAC53608 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 16-pin WQFN (RTE), 3.00 mm x 3.00 mm |
| Resolution | 10 bits; condition: DAC53608 |
| Number of DAC Channels | 8; condition: Octal DAC device family |
| Output Type | Buffered voltage output; condition: DACx3608 family |
| Supply Voltage Range | 1.8 V to 5.5 V; condition: Recommended operating condition, VDD to AGND |
| Reference Input Voltage Range | 1.8 V to VDD; condition: Recommended operating condition, VREFIN to AGND |
| Operating Temperature Range | -40 °C to +125 °C; condition: Ambient temperature, TA |
| INL Relative Accuracy | min -1 LSB, max +1 LSB; condition: DAC53608, 2.7 V <= VDD <= 5.5 V |
| INL Relative Accuracy | min -1 LSB, max +1 LSB; condition: DAC53608, 1.8 V <= VDD <= 2.7 V |
| DNL Differential Nonlinearity | min -1 LSB, max +1 LSB; condition: DAC53608, 2.7 V <= VDD <= 5.5 V |
| DNL Differential Nonlinearity | min -1 LSB, max +1 LSB; condition: DAC53608, 1.8 V <= VDD <= 2.7 V |
| Zero Code Error | typ 6 mV, max 12 mV; condition: 2.7 V <= VDD <= 5.5 V, code 0d into DAC |
| Zero Code Error | typ 6 mV, max 12 mV; condition: 1.8 V <= VDD <= 2.7 V, code 0d into DAC |
| Zero Code Error Temperature Coefficient | typ ±5 µV/°C; condition: Specified electrical characteristics |
| Offset Error | min -0.5 %FSR, typ 0.25 %FSR, max 0.5 %FSR; condition: 2.7 V <= VDD <= 5.5 V |
| Offset Error | min -0.5 %FSR, typ 0.25 %FSR, max 0.5 %FSR; condition: 1.8 V <= VDD <= 2.7 V |
| Gain Error | min -0.5 %FSR, typ 0.25 %FSR, max 0.5 %FSR; condition: 2.7 V <= VDD <= 5.5 V |
| Gain Error | min -0.5 %FSR, typ 0.25 %FSR, max 0.5 %FSR; condition: 1.8 V <= VDD <= 2.7 V |
| Full Scale Error | min -0.5 %FSR, typ 0.25 %FSR, max 0.5 %FSR; condition: 2.7 V <= VDD <= 5.5 V, code 1023d into DAC, no headroom |
| Full Scale Error | min -1 %FSR, typ 0.5 %FSR, max 1 %FSR; condition: 1.8 V <= VDD <= 2.7 V, code 1023d into DAC, no headroom |
| Output Voltage Range | 0 V to 5.5 V; condition: VOUTX output voltage |
| Capacitive Load | typ 1 nF; condition: RL = infinite; not production tested |
| Capacitive Load | typ 2 nF; condition: RL = 5 kΩ; not production tested |
| Load Regulation | typ 0.1 mV/mA; condition: DAC at midscale, -10 mA <= IOUT <= 10 mA, VDD = 5.5 V |
| Short Circuit Current | typ 10 mA; condition: VDD = 1.8 V, per channel full-scale output shorted to AGND or zero-scale output shorted to VDD |
| Short Circuit Current | typ 25 mA; condition: VDD = 2.7 V, per channel full-scale output shorted to AGND or zero-scale output shorted to VDD |
| Short Circuit Current | typ 50 mA; condition: VDD = 5.5 V, per channel full-scale output shorted to AGND or zero-scale output shorted to VDD |
| Output Voltage Headroom | typ 0.05 V; condition: To VDD, DAC output unloaded |
| Output Voltage Settling Time | typ 10 µs; condition: 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10% FSR, RL = 5 kΩ, CL = 200 pF, VDD = 5.5 V |
| Slew Rate | typ 0.6 V/µs; condition: RL = 5 kΩ, CL = 200 pF, VDD = 5.5 V |
| Power-On Glitch Magnitude | typ 110 mV; condition: RL = 5 kΩ, CL = 200 pF |
| Output Noise | typ 40 µVpp; condition: 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V |
| Output Noise | typ 0.05 mVrms; condition: 0.1 Hz to 100 kHz bandwidth, DAC at midscale, VDD = 5.5 V |
| Output Noise Density | typ 0.2 µV/√Hz; condition: Measured at 1 kHz, DAC at midscale, VDD = 5.5 V |
| AC Power Supply Rejection Ratio | typ -71 dB; condition: 200 mV 50/60 Hz sinewave superimposed on power supply voltage, DAC at midscale |
| Reference Input Impedance | typ 12.5 kΩ; condition: All channels powered on |
| Reference Input Capacitance | typ 50 pF; condition: Voltage reference input |
| Digital Feedthrough | typ 20 nV-s; condition: SCLK = 1 MHz, DAC output static at midscale |
| Pin Capacitance | typ 10 pF; condition: Per digital input pin |
| Supply Current | typ 3 mA, max 5 mA; condition: Normal mode, all DACs at full scale, serial interface static |
| Power-Down Supply Current | typ 50 µA; condition: All DACs powered down |
| Serial Interface | I2C standard mode, fast mode, fast+ mode; condition: Supports 100 kbps, 400 kbps, and 1 Mbps operation |
| I2C Standard Mode SCLK Frequency | max 0.1 MHz; condition: 1.8 V <= VDD <= 5.5 V, -40 °C <= TA <= +125 °C |
| Absolute Maximum Supply Voltage | min -0.3 V, max 6 V; condition: VDD to AGND |
| HBM ESD Rating | ±1000 V; condition: Human body model, ANSI/ESDA/JEDEC JS-001, all pins |
| CDM ESD Rating | ±500 V; condition: Charged device model, JEDEC JESD22-C101, all pins |
| Datasheet Status | request_only |
Product Overview
The DAC53608 is a Texas Instruments octal voltage-output DAC for Signal_Chain designs requiring multiple buffered voltage outputs from one device. It provides 8 DAC channels with 10-bit resolution and buffered voltage outputs, with output voltage specified from 0 V to 5.5 V. The device operates from a 1.8 V to 5.5 V supply and accepts a reference input from 1.8 V to VDD.
Accuracy specifications for the DAC53608 include INL and DNL limits of -1 LSB to +1 LSB across both 2.7 V to 5.5 V and 1.8 V to 2.7 V VDD ranges. Offset error and gain error are specified at -0.5 %FSR minimum, 0.25 %FSR typical, and 0.5 %FSR maximum for both supply ranges. Full-scale error differs by range, with ±0.5 %FSR limits at 2.7 V to 5.5 V and ±1 %FSR limits at 1.8 V to 2.7 V.
The device is supplied in a 16-pin WQFN (RTE), 3.00 mm x 3.00 mm package and operates across -40 °C to +125 °C ambient temperature. Interface support includes I2C standard mode, fast mode, and fast+ mode, covering 100 kbps, 400 kbps, and 1 Mbps operation.
Key Features
- 10-bit DAC53608 resolution
- Eight buffered voltage-output DAC channels
- 1.8 V to 5.5 V supply range
- Reference input range from 1.8 V to VDD
- -40 °C to +125 °C ambient operation
- INL and DNL specified to ±1 LSB
- 0 V to 5.5 V output voltage range
- Typical 10 µs output settling time
- I2C standard, fast, and fast+ modes
- Typical 3 mA normal-mode supply current
Typical Applications
- Multi-channel voltage generation
- I2C-controlled analog outputs
- Signal-chain bias adjustment
- Reference-driven DAC output stages
- Low-voltage embedded control systems
- Temperature-rated industrial signal paths
- Buffered control voltage outputs
Procurement Notes
When requesting a quote for DAC53608, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of converter is the DAC53608?
The DAC53608 is an octal voltage-output DAC from Texas Instruments. It provides 8 DAC channels with 10-bit resolution and buffered voltage outputs, placing it in the Signal_Chain category.
What supply voltage range does the DAC53608 support?
The recommended VDD operating range for the DAC53608 is 1.8 V to 5.5 V. Its reference input voltage range is specified from 1.8 V to VDD.
What package is specified for the DAC53608?
The listed package for the DAC53608 is a 16-pin WQFN (RTE) package measuring 3.00 mm x 3.00 mm.
Which serial interface modes are supported by the DAC53608?
The DAC53608 supports I2C standard mode, fast mode, and fast+ mode. The extracted interface facts list operation at 100 kbps, 400 kbps, and 1 Mbps.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.