Specifications
| Type | Description |
|---|---|
| Part Number | SN74AVC1T45_Level-Shifter |
| Manufacturer | Texas Instruments |
| Product Type | I2C Switch |
| Category | Signal Chain |
| Package / Case | DCK SOT-SC70-6 2.0 mm x 2.1 mm; DBV SOT-23-6 2.9 mm x 2.8 mm; DRL SOT-5X3-6 1.6 mm x 1.6 mm; YZP DSBGA-6 1.75 mm x 1.25 mm |
| Supply voltage A operating range | 1.2-3.6 V; VCCA recommended operating conditions |
| Supply voltage B operating range | 1.2-3.6 V; VCCB recommended operating conditions |
| Supply voltage A absolute maximum | -0.5 to 4.6 V; VCCA absolute maximum rating |
| Supply voltage B absolute maximum | -0.5 to 4.6 V; VCCB absolute maximum rating |
| A-port input voltage absolute maximum | -0.5 to 4.6 V; input voltage on I/O port A |
| B-port input voltage absolute maximum | -0.5 to 4.6 V; input voltage on I/O port B |
| Control input voltage absolute maximum | -0.5 to 4.6 V; DIR control input |
| High-impedance output voltage absolute maximum | -0.5 to 4.6 V; voltage applied to output in high-impedance or power-off state |
| Active output voltage absolute maximum | -0.5 to VCCO + 0.5 V; voltage applied to output in high or low state; may exceed up to 6.5 V maximum if output current rating is observed |
| Input clamp current | -50 mA; VI < 0 V |
| Output clamp current | -50 mA; VO < 0 V |
| Continuous output current | -50 to 50 mA; absolute maximum rating |
| Continuous current through supply or ground | -100 to 100 mA; through VCCA, VCCB, or GND |
| Junction temperature absolute maximum | 150 °C; Tj |
| Storage temperature | -65 to 150 °C; Tstg |
| HBM ESD rating | ±2000 V; human body model per ANSI/ESDA/JEDEC JS-001 |
| CDM ESD rating | ±1000 V; charged device model per JEDEC JESD22-C101 |
| Machine model ESD rating | 200 V; per A115-A |
| High-level input voltage | 0.65 x VCCI; data inputs, VCCI = 1.2 V to 1.95 V |
| High-level input voltage | 1.6 V; data inputs, VCCI = 1.95 V to 2.7 V |
| High-level input voltage | 2 V; data inputs, VCCI = 2.7 V to 3.6 V |
| Low-level input voltage | 0.35 x VCCI; data inputs, VCCI = 1.2 V to 1.95 V |
| Low-level input voltage | 0.7 V; data inputs, VCCI = 1.95 V to 2.7 V |
| Low-level input voltage | 0.8 V; data inputs, VCCI = 2.7 V to 3.6 V |
| Control input reference | Referenced to VCCA; DIR input circuit |
| Input voltage recommended range | 0 to 3.6 V; VI |
| Output voltage recommended range | 0 to VCCO; active state |
| Output voltage recommended range | 0 to 3.6 V; 3-state |
| High-level output current | -3 mA; VCCO = 1.2 V |
| High-level output current | -6 mA; VCCO = 1.4 V to 1.6 V |
| High-level output current | -8 mA; VCCO = 1.65 V to 1.95 V |
| High-level output current | -9 mA; VCCO = 2.3 V to 2.7 V |
| High-level output current | -12 mA; VCCO = 3 V to 3.6 V |
| Low-level output current | 3 mA; VCCO = 1.2 V |
| Low-level output current | 6 mA; VCCO = 1.4 V to 1.6 V |
| Low-level output current | 8 mA; VCCO = 1.65 V to 1.95 V |
| Low-level output current | 9 mA; VCCO = 2.3 V to 2.7 V |
| Low-level output current | 12 mA; VCCO = 3 V to 3.6 V |
| Input transition rise and fall time | 5 ns/V; recommended operating condition |
| Operating free-air temperature | -40 to 85 °C; TA |
| Maximum data rate | 500 Mbps; 1.8 V to 3.3 V translation |
| Maximum data rate | 320 Mbps; less than 1.8 V to 3.3 V translation |
| Maximum data rate | 320 Mbps; translate to 2.5 V or 1.8 V |
| Maximum data rate | 280 Mbps; translate to 1.5 V |
| Maximum data rate | 240 Mbps; translate to 1.2 V |
| Voltage isolation feature | Both ports high-impedance if either VCC input is at GND; VCC isolation |
| Partial-power-down support | Ioff circuitry disables outputs to prevent current backflow; power-down operation |
| I/O voltage tolerance | 4.6 V tolerant; A and B I/O ports |
| Direction logic behavior | DIR activates B-port outputs for A-to-B transfer or A-port outputs for B-to-A transfer; asynchronous bus communication |
| Pin 1 function | VCCA; DBV, DCK, DRL packages; A-port supply voltage |
| Pin 2 function | GND; DBV, DCK, DRL packages |
| Pin 3 function | A; DBV, DCK, DRL packages; input/output A referenced to VCCA |
| Pin 4 function | B; DBV, DCK, DRL packages; input/output B referenced to VCCB |
| Pin 5 function | DIR; DBV, DCK, DRL packages; direction control signal |
| Pin 6 function | VCCB; DBV, DCK, DRL packages; B-port supply voltage |
| Thermal resistance junction-to-ambient | 183.4 °C/W; DBV SOT-23 package |
| Thermal resistance junction-to-ambient | 211.4 °C/W; DCK SOT-SC70 package |
| Thermal resistance junction-to-ambient | 236.2 °C/W; DRL SOT-5X3 package |
| Thermal resistance junction-to-ambient | 130 °C/W; YZP DSBGA package |
| Output high voltage | Min VCCO - 0.2 V; IOH = -100 µA, VCCA = 1.2 V to 3.6 V, VCCB = 1.2 V to 3.6 V |
| Output low voltage | Max 0.2 V; IOL = 100 µA, VCCA = 1.2 V to 3.6 V, VCCB = 1.2 V to 3.6 V |
| DIR input leakage current | Typ ±0.025 µA, max 0.25 µA at 25°C; max ±1 µA over -40°C to 85°C; VI = VCCA or GND, VCCA = 1.2 V to 3.6 V, VCCB = 1.2 V to 3.6 V |
| Power-off leakage current | Typ ±0.1 µA, max ±1 µA at 25°C; max ±5 µA over -40°C to 85°C; A port, VCCA = 0 V, VCCB = 0 V to 3.6 V, VI or VO = 0 V to 3.6 V |
| Power-off leakage current | Typ ±0.1 µA, max ±1 µA at 25°C; max ±5 µA over -40°C to 85°C; B port, VCCA = 0 V to 3.6 V, VCCB = 0 V, VI or VO = 0 V to 3.6 V |
| Output high-impedance leakage current | Typ ±0.5 µA, max ±2.5 µA at 25°C; max ±5 µA over -40°C to 85°C; B port, VCCA = 0 V, VCCB = 3.6 V, VI or VO = 0 V to 3.6 V |
| Output high-impedance leakage current | Typ ±0.5 µA, max ±2.5 µA at 25°C; max ±5 µA over -40°C to 85°C; A port, VCCA = 3.6 V, VCCB = 0 V, VI or VO = 0 V to 3.6 V |
| Control input capacitance | Typ 2.5 pF; VI = 3.3 V or GND, VCCA = 3.3 V, VCCB = 3.3 V |
| I/O port capacitance | Typ 6 pF; VO = 3.3 V or GND, VCCA = 3.3 V, VCCB = 3.3 V |
| Propagation delay A to B | Typ 3.3 ns; tPLH/tPHL, VCCA = 1.2 V, VCCB = 1.2 V |
| Propagation delay A to B | Typ 2.4 ns; tPLH/tPHL, VCCA = 1.2 V, VCCB = 3.3 V |
| Propagation delay B to A | Typ 3.3 ns; tPLH/tPHL, VCCA = 1.2 V, VCCB = 1.2 V |
| Propagation delay B to A | Typ 2.7 ns; tPLH/tPHL, VCCA = 1.2 V, VCCB = 3.3 V |
| Datasheet Status | request_only |
Product Overview
SN74AVC1T45_Level-Shifter from Texas Instruments is an Interface single-bit dual-supply bus transceiver. The A port is referenced to VCCA and the B port is referenced to VCCB, with both supply rails specified for 1.2-3.6 V operation. Direction is controlled by the DIR input, which is referenced to VCCA and selects either A-to-B transfer with B-port outputs active or B-to-A transfer with A-port outputs active.
The device is available in DCK SOT-SC70-6, DBV SOT-23-6, DRL SOT-5X3-6, and YZP DSBGA-6 package options. Pin functions for DBV, DCK, and DRL packages assign VCCA to pin 1, GND to pin 2, A to pin 3, B to pin 4, DIR to pin 5, and VCCB to pin 6.
Specified behavior includes VCC isolation, Ioff partial-power-down support, 4.6 V tolerant A and B I/O ports, and operation over -40 to 85 °C. Maximum data-rate ratings span 500 Mbps for 1.8 V to 3.3 V translation down to 240 Mbps when translating to 1.2 V.
Key Features
- Single-bit dual-supply bus transceiver architecture
- VCCA and VCCB operate from 1.2-3.6 V
- A and B I/O ports are 4.6 V tolerant
- DIR selects A-to-B or B-to-A transfer
- Both ports high-impedance if either VCC is grounded
- Ioff circuitry disables outputs during power-down
- Maximum 500 Mbps for 1.8 V to 3.3 V translation
- Specified operation from -40 to 85 °C
- Available in SC70, SOT-23, SOT-5X3, and DSBGA packages
- Typical 2.4 ns A-to-B delay at 1.2 V to 3.3 V
Typical Applications
- Single-bit voltage-level translation
- A-to-B bus signal transfer
- B-to-A bus signal transfer
- Asynchronous bus communication
- Dual-supply interface bridging
- Partial-power-down signal isolation
- 1.2 V to 3.3 V translation
- Compact interface assemblies
Procurement Notes
When requesting a quote for SN74AVC1T45_Level-Shifter, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What supply range does SN74AVC1T45_Level-Shifter support?
The device has separate VCCA and VCCB supply rails, and both are specified for 1.2-3.6 V operation under recommended operating conditions. The A port is referenced to VCCA, while the B port is referenced to VCCB.
How is the transfer direction controlled on this transceiver?
Direction is controlled by the DIR input, which is referenced to VCCA. The DIR logic activates B-port outputs for A-to-B transfer or A-port outputs for B-to-A transfer during asynchronous bus communication.
What happens if one supply input is at ground?
The voltage isolation feature places both ports in a high-impedance state if either VCC input is at GND. The device also includes Ioff circuitry that disables outputs during power-down to prevent current backflow.
Which package options are listed for this part?
The listed packages are DCK SOT-SC70-6 at 2.0 mm x 2.1 mm, DBV SOT-23-6 at 2.9 mm x 2.8 mm, DRL SOT-5X3-6 at 1.6 mm x 1.6 mm, and YZP DSBGA-6 at 1.75 mm x 1.25 mm.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.