Specifications
| Type | Description |
|---|---|
| Part Number | SN74LVC1G04 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Component Type | Other |
| Package Case | DBV SOT-23-5 2.9mm x 2.8mm package / 2.9mm x 1.6mm body; DCK SC70-5 2.0mm x 2.1mm package / 2.0mm x 1.25mm body; DPW X2SON-5 0.8mm x 0.8mm package/body; DRL SOT-5X3-5 1.6mm x 1.6mm package / 1.6mm x 1.2mm body; DRY USON-6 1.45mm x 1.0mm package/body; DSF X2SON-6 1.0mm x 1.0mm package/body; YZP DSBGA-5 1.75mm x 1.75mm package / 1.75mm x 1.25mm body; YZV DSBGA-4 1.25mm x 1.25mm package/body |
| Logic function | Y = NOT A; condition: Single inverter gate |
| Operating supply voltage | 1.65-5.5 V; condition: VCC operating range |
| 5 V VCC operation | Supported; condition: Feature list |
| Input overvoltage tolerance | Inputs accept voltages up to 5.5 V; condition: Allows down translation to VCC |
| Maximum propagation delay | 3.3 ns; condition: VCC=3.3 V |
| Maximum ICC | 10 uA; condition: Low power consumption feature |
| Output drive current | +/-24 mA; condition: VCC=3.3 V |
| Partial-power-down support | Ioff supports live insertion, partial-power-down mode, and back-drive protection; condition: Feature list |
| Latch-up performance | >100 mA; condition: Per JESD 78, Class II |
| HBM ESD protection | 2000 V; condition: JESD 22 / A114-A feature list |
| Machine model ESD protection | 200 V; condition: JESD 22 / A115-A feature list |
| CDM ESD protection | 1000 V; condition: JESD 22 / C101 feature list |
| Pin A | Input; condition: DBV/DCK/DRL/DSF/DRY pin 2; YZP B1; YZV A1; DPW pin 2 |
| Pin Y | Output; condition: DBV/DCK/DRL/DSF/DRY pin 4; YZP C2; YZV B2; DPW pin 4 |
| Pin VCC | Power terminal; condition: DBV/DCK/DRL pin 5; DSF/DRY pin 6; YZP A2; YZV A2; DPW pin 5 |
| Pin GND | Ground; condition: DBV/DCK/DRL/DSF/DRY pin 3; YZP C1; YZV B1; DPW pin 3 |
| Absolute maximum supply voltage | -0.5 to 6.5 V; condition: VCC supply voltage range |
| Absolute maximum input voltage | -0.5 to 6.5 V; condition: VI input voltage range |
| Absolute maximum output voltage, high-impedance or power-off | -0.5 to 6.5 V; condition: VO applied to any output in high-impedance or power-off state |
| Absolute maximum output voltage, high or low state | -0.5 to VCC + 0.5 V; condition: VO applied to any output in high or low state |
| Input clamp current | -50 mA; condition: VI < 0 V |
| Output clamp current | -50 mA; condition: VO < 0 V |
| Continuous output current | +/-50 mA; condition: IO absolute maximum rating |
| Continuous current through VCC or GND | +/-100 mA; condition: Absolute maximum rating |
| Storage temperature | -65 to 150 degC; condition: Tstg absolute maximum rating |
| ESD rating HBM | +/-2000 V; condition: ANSI/ESDA/JEDEC JS-001, all pins |
| ESD rating CDM | +/-1000 V; condition: JEDEC JESD22-C101, all pins |
| Recommended supply voltage | 1.65-5.5 V; condition: Operating VCC |
| Data retention supply voltage | 1.5 V; condition: VCC, data retention only |
| High-level input voltage | 0.65 x VCC min; condition: VCC=1.65 V to 1.95 V |
| High-level input voltage | 1.7 V min; condition: VCC=2.3 V to 2.7 V |
| High-level input voltage | 2.0 V min; condition: VCC=3.0 V to 3.6 V |
| High-level input voltage | 0.7 x VCC min; condition: VCC=4.5 V to 5.5 V |
| Low-level input voltage | 0.35 x VCC max; condition: VCC=1.65 V to 1.95 V |
| Low-level input voltage | 0.7 V max; condition: VCC=2.3 V to 2.7 V |
| Low-level input voltage | 0.8 V max; condition: VCC=3.0 V to 3.6 V |
| Low-level input voltage | 0.3 x VCC max; condition: VCC=4.5 V to 5.5 V |
| Recommended input voltage | 0 to 5.5 V; condition: VI |
| Recommended output voltage | 0 to VCC V; condition: VO |
| High-level output current | -4 mA; condition: VCC=1.65 V |
| High-level output current | -8 mA; condition: VCC=2.3 V |
| High-level output current | -16 mA or -24 mA; condition: VCC=3 V |
| High-level output current | -32 mA; condition: VCC=4.5 V |
| Low-level output current | 4 mA; condition: VCC=1.65 V |
| Low-level output current | 8 mA; condition: VCC=2.3 V |
| Low-level output current | 16 mA or 24 mA; condition: VCC=3 V |
| Low-level output current | 32 mA; condition: VCC=4.5 V |
| Input transition rise or fall rate | 20 ns/V max; condition: VCC=1.8 V +/-0.15 V or 2.5 V +/-0.2 V |
| Input transition rise or fall rate | 10 ns/V max; condition: VCC=3.3 V +/-0.3 V |
| Input transition rise or fall rate | 5 ns/V max; condition: VCC=5 V +/-0.5 V |
| Operating free-air temperature | -40 to 125 degC; condition: TA |
| VOH | VCC - 0.1 V min; condition: IOH=-100 uA, VCC=1.65 V to 5.5 V, -40 to 85 degC and -40 to 125 degC |
| VOH | 1.2 V min; condition: IOH=-4 mA, VCC=1.65 V, -40 to 85 degC and -40 to 125 degC |
| VOH | 1.9 V min; condition: IOH=-8 mA, VCC=2.3 V, -40 to 85 degC and -40 to 125 degC |
| VOH | 2.4 V min; condition: IOH=-16 mA, VCC=3 V, -40 to 85 degC and -40 to 125 degC |
| VOH | 2.3 V min; condition: IOH=-24 mA, VCC=3 V, -40 to 85 degC and -40 to 125 degC |
| VOH | 3.8 V min; condition: IOH=-32 mA, VCC=4.5 V, -40 to 85 degC and -40 to 125 degC |
| VOL | 0.1 V max; condition: IOL=100 uA, VCC=1.65 V to 5.5 V, -40 to 85 degC and -40 to 125 degC |
| VOL | 0.45 V max; condition: IOL=4 mA, VCC=1.65 V, -40 to 85 degC and -40 to 125 degC |
| VOL | 0.3 V max; condition: IOL=8 mA, VCC=2.3 V, -40 to 85 degC and -40 to 125 degC |
| VOL | 0.4 V max; condition: IOL=16 mA, VCC=3 V, -40 to 85 degC and -40 to 125 degC |
| VOL | 0.55 V max; condition: IOL=24 mA, VCC=3 V, -40 to 85 degC and -40 to 125 degC |
| VOL | 0.55 V max; condition: IOL=32 mA, VCC=4.5 V, -40 to 85 degC and -40 to 125 degC |
| Input leakage current | +/-5 uA max; condition: II, A input, VI=5.5 V or GND, VCC=0 to 5.5 V |
| Power-off leakage current | +/-10 uA max; condition: Ioff, VI or VO=5.5 V, VCC=0 V |
| Supply current | 10 uA max; condition: ICC, VI=5.5 V or GND, IO=0, VCC=1.65 V to 5.5 V |
| Delta supply current | 500 uA max; condition: Delta ICC, one input at VCC - 0.6 V, other inputs at VCC or GND, VCC=3 V to 5.5 V |
| Input capacitance | 3.5 pF typ; condition: Ci, VI=VCC or GND, VCC=3.3 V |
| Propagation delay | 2-6.4 ns; condition: tpd A to Y, CL=15 pF, VCC=1.8 V +/-0.15 V, -40 to 85 degC |
| Propagation delay | 1-4.2 ns; condition: tpd A to Y, CL=15 pF, VCC=2.5 V +/-0.2 V, -40 to 85 degC |
| Propagation delay | 0.7-3.3 ns; condition: tpd A to Y, CL=15 pF, VCC=3.3 V +/-0.3 V, -40 to 85 degC |
| Propagation delay | 0.7-3.1 ns; condition: tpd A to Y, CL=15 pF, VCC=5 V +/-0.5 V, -40 to 85 degC |
| Propagation delay | 3-7.5 ns; condition: tpd A to Y, CL=30 pF or 50 pF, VCC=1.8 V +/-0.15 V, -40 to 85 degC |
| Propagation delay | 1.4-5.2 ns; condition: tpd A to Y, CL=30 pF or 50 pF, VCC=2.5 V +/-0.2 V, -40 to 85 degC |
| Propagation delay | 1-4.2 ns; condition: tpd A to Y, CL=30 pF or 50 pF, VCC=3.3 V +/-0.3 V, -40 to 85 degC |
| Propagation delay | 1-3.7 ns; condition: tpd A to Y, CL=30 pF or 50 pF, VCC=5 V +/-0.5 V, -40 to 85 degC |
| Propagation delay | 2-6.4 ns; condition: tpd A to Y, CL=15 pF, VCC=1.8 V +/-0.15 V, -40 to 125 degC |
| Propagation delay | 1-4.2 ns; condition: tpd A to Y, CL=15 pF, VCC=2.5 V +/-0.2 V, -40 to 125 degC |
| Propagation delay | 0.7-3.3 ns; condition: tpd A to Y, CL=15 pF, VCC=3.3 V +/-0.3 V, -40 to 125 degC |
| Propagation delay | 0.7-3.1 ns; condition: tpd A to Y, CL=15 pF, VCC=5 V +/-0.5 V, -40 to 125 degC |
| Propagation delay | 3-7.5 ns; condition: tpd A to Y, CL=30 pF or 50 pF, VCC=1.8 V +/-0.15 V, -40 to 125 degC |
| Propagation delay | 1.4-5.2 ns; condition: tpd A to Y, CL=30 pF or 50 pF, VCC=2.5 V +/-0.2 V, -40 to 125 degC |
| Propagation delay | 1-4.2 ns; condition: tpd A to Y, CL=30 pF or 50 pF, VCC=3.3 V +/-0.3 V, -40 to 125 degC |
| Propagation delay | 1-3.7 ns; condition: tpd A to Y, CL=30 pF or 50 pF, VCC=5 V +/-0.5 V, -40 to 125 degC |
| Power dissipation capacitance | 16 pF typ; condition: Cpd, f=10 MHz, VCC=1.8 V |
| Power dissipation capacitance | 18 pF typ; condition: Cpd, f=10 MHz, VCC=2.5 V |
| Power dissipation capacitance | 18 pF typ; condition: Cpd, f=10 MHz, VCC=3.3 V |
| Power dissipation capacitance | 20 pF typ; condition: Cpd, f=10 MHz, VCC=5.0 V |
| Datasheet Status | request_only |
Product Overview
The SN74LVC1G04 is a Texas Instruments single inverter logic gate in the Signal_Chain category. Its logic function is Y = NOT A, with one A input and one Y output. The device operates across a 1.65 V to 5.5 V VCC range and supports 5 V VCC operation. Inputs accept voltages up to 5.5 V, enabling down translation to the active VCC rail.
Electrical limits include 10 uA maximum supply current, +/-5 uA maximum input leakage, +/-10 uA maximum power-off leakage, and 3.5 pF typical input capacitance at VCC = 3.3 V. Propagation delay is specified across supply rails and load capacitances, including 0.7 ns to 3.3 ns at VCC = 3.3 V +/-0.3 V with CL = 15 pF.
Package choices include DBV SOT-23-5, DCK SC70-5, DPW X2SON-5, DRL SOT-5X3-5, DRY USON-6, DSF X2SON-6, YZP DSBGA-5, and YZV DSBGA-4. The Ioff feature supports live insertion, partial-power-down mode, and back-drive protection, supporting use in compact logic inversion and voltage-domain interface circuits.
Key Features
- Single inverter gate implements Y = NOT A
- Operates from 1.65 V to 5.5 V VCC
- Supports 5 V VCC operation
- Inputs accept voltages up to 5.5 V
- 3.3 ns maximum propagation delay at 3.3 V
- 10 uA maximum ICC supply current
- +/-24 mA output drive at 3.3 V
- Ioff supports live insertion and back-drive protection
- -40 to 125 degC operating free-air temperature
- HBM ESD rating is +/-2000 V
Typical Applications
- Logic signal inversion
- Voltage-level down translation
- Partial-power-down logic interfaces
- Live-insertion protected circuits
- Back-drive protected signal paths
- Compact board-level logic gating
- Low-power digital control lines
Procurement Notes
When requesting a quote for SN74LVC1G04, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What logic function does the SN74LVC1G04 provide?
The SN74LVC1G04 is a single inverter logic gate. Its specified logic function is Y = NOT A, with A as the input and Y as the output.
What supply voltage range is recommended for this device?
The recommended operating VCC range is 1.65 V to 5.5 V. A 1.5 V supply is specified for data retention only, and 5 V VCC operation is supported.
Can the input tolerate voltages above the active VCC rail?
Yes. The extracted datasheet facts state that inputs accept voltages up to 5.5 V, allowing down translation to VCC. The recommended input voltage range is 0 V to 5.5 V.
What packages are listed for the SN74LVC1G04?
Listed package options include DBV SOT-23-5, DCK SC70-5, DPW X2SON-5, DRL SOT-5X3-5, DRY USON-6, DSF X2SON-6, YZP DSBGA-5, and YZV DSBGA-4.
What protection does the Ioff feature provide?
The Ioff feature supports live insertion, partial-power-down mode, and back-drive protection. Power-off leakage is specified as +/-10 uA maximum when VI or VO is 5.5 V and VCC is 0 V.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.