Specifications
| Type | Description |
|---|---|
| Part Number | SN74AUP1G34 |
| Manufacturer | Texas Instruments |
| Product Type | Single Buffer Gate |
| Category | Logic |
| Package Case | SOT-5 1.60 mm x 1.20 mm; USON-6 1.45 mm x 1.00 mm; X2SON-4 0.80 mm x 0.80 mm; DSBGA-4 0.79 mm x 0.79 mm |
| Logic Function | Y = A; positive logic buffer |
| Supply Voltage Range | 0.8 to 3.6 V; recommended operating conditions |
| Static Supply Current | 0.9 uA max; feature summary |
| Power Dissipation Capacitance | 4.1 pF typ; VCC = 3.3 V, f = 10 MHz, TA = 25°C |
| Input Capacitance | 1.5 pF typ; VI = VCC or GND, VCC = 0 V or 3.6 V |
| Output Capacitance | 2.5 pF typ; VO = GND, VCC = 0 V |
| Input Hysteresis | 250 mV typ; VCC = 3.3 V |
| Overshoot and Undershoot | <10% of VCC; low-noise feature |
| I/O Tolerance | 3.6 V tolerant; mixed-mode signal operation |
| Ioff Support | Supported; live insertion, partial power-down mode, and back-drive protection |
| Propagation Delay | 1.4 ns min, 2 ns typ, 3.2 ns max at TA = 25°C; 0.6 ns min, 4.1 ns max over temperature; CL = 5 pF, VCC = 3.3 V ±0.3 V, A to Y |
| Propagation Delay | 2 ns min, 2.4 ns typ, 3.8 ns max at TA = 25°C; 1.1 ns min, 4.8 ns max over temperature; CL = 10 pF, VCC = 3.3 V ±0.3 V, A to Y |
| Propagation Delay | 2.3 ns min, 2.9 ns typ, 4.2 ns max at TA = 25°C; 1.5 ns min, 5 ns max over temperature; CL = 15 pF, VCC = 3.3 V ±0.3 V, A to Y |
| Propagation Delay | 3.3 ns min, 4 ns typ, 5.3 ns max at TA = 25°C; 2.5 ns min, 6.5 ns max over temperature; CL = 30 pF, VCC = 3.3 V ±0.3 V, A to Y |
| High-Level Input Voltage | VCC; VCC = 0.8 V |
| High-Level Input Voltage | 0.65 x VCC; VCC = 1.1 V to 1.95 V |
| High-Level Input Voltage | 1.6 V; VCC = 2.3 V to 2.7 V |
| High-Level Input Voltage | 2 V; VCC = 3 V to 3.6 V |
| Low-Level Input Voltage | 0 V; VCC = 0.8 V |
| Low-Level Input Voltage | 0.35 x VCC; VCC = 1.1 V to 1.95 V |
| Low-Level Input Voltage | 0.7 V; VCC = 2.3 V to 2.7 V |
| Low-Level Input Voltage | 0.9 V; VCC = 3 V to 3.6 V |
| Input Voltage Range | 0 to 3.6 V; recommended operating conditions |
| Output Voltage Range | 0 to VCC V; recommended operating conditions |
| High-Level Output Current | -20 uA; VCC = 0.8 V |
| High-Level Output Current | -1.1 mA; VCC = 1.1 V |
| High-Level Output Current | -1.7 mA; VCC = 1.4 V |
| High-Level Output Current | -1.9 mA; VCC = 1.65 V |
| High-Level Output Current | -3.1 mA; VCC = 2.3 V |
| High-Level Output Current | -4 mA; VCC = 3 V |
| Low-Level Output Current | 20 uA; VCC = 0.8 V |
| Low-Level Output Current | 1.1 mA; VCC = 1.1 V |
| Low-Level Output Current | 1.7 mA; VCC = 1.4 V |
| Low-Level Output Current | 1.9 mA; VCC = 1.65 V |
| Low-Level Output Current | 3.1 mA; VCC = 2.3 V |
| Low-Level Output Current | 4 mA; VCC = 3 V |
| Input Transition Rise or Fall Rate | 200 ns/V max; VCC = 0.8 V to 3.6 V |
| Operating Free-Air Temperature | -40 to 85 °C; recommended operating conditions |
| Absolute Maximum Supply Voltage | -0.5 to 4.6 V; over operating free-air temperature range |
| Absolute Maximum Input Voltage | -0.5 to 4.6 V; over operating free-air temperature range |
| Absolute Maximum Output Voltage High-Impedance or Power-Off | -0.5 to 4.6 V; voltage applied to any output in high-impedance or power-off state |
| Absolute Maximum Output Voltage High or Low State | -0.5 to VCC + 0.5 V; output in high or low state |
| Input Clamp Current | -50 mA; VI < 0 |
| Output Clamp Current | -50 mA; VO < 0 |
| Continuous Output Current | ±20 mA; absolute maximum rating |
| Continuous Current Through VCC or GND | ±50 mA; absolute maximum rating |
| Storage Temperature Range | -65 to 150 °C; handling ratings |
| ESD Rating HBM | 2000 V; human body model per ANSI/ESDA/JEDEC JS-001, all pins |
| ESD Rating CDM | 1000 V; charged device model per JEDEC JESD22-C101, all pins |
| Latch-Up Performance | >100 mA; per JESD78, Class II |
| Datasheet Status | request_only |
Product Overview
The SN74AUP1G34 is a Texas Instruments low-power single buffer gate from the advanced ultra-low-power 74AUP1G logic family. It implements a positive logic buffer function with the logic relationship Y = A, providing true non-inverting signal buffering. The device is designed for low-power, mixed-signal applications requiring minimal static power consumption. Its recommended operating supply range is 0.8 V to 3.6 V, with support for 3.6 V tolerant I/O for mixed-mode signal operation. The SN74AUP1G34 features Ioff partial power-down protection, enabling live insertion and back-drive protection in battery-powered and hot-swap systems. It is available in multiple compact package options including SOT-5, USON-6, X2SON-4, and DSBGA-4, making it suitable for space-constrained board designs. The device delivers a maximum static supply current of only 0.9 uA, input hysteresis of 250 mV typical at 3.3 V, and HBM ESD protection of 2000 V on all pins, ensuring robust operation across a -40°C to 85°C temperature range.
Key Features
- Positive logic buffer function with Y equals A
- 0.8 V to 3.6 V recommended supply range
- 0.9 uA maximum static supply current
- 3.6 V tolerant I/O for mixed-mode signal operation
- Ioff supports live insertion and partial power-down protection
- 250 mV typical input hysteresis at VCC 3.3 V
- Overshoot and undershoot below 10% of VCC
- 1.5 pF typical input capacitance
- 4.1 pF typical power dissipation capacitance
- -40°C to 85°C operating free-air temperature
- HBM ESD rating of 2000 V on all pins
- Latch-up performance greater than 100 mA per JESD78
Typical Applications
- Positive logic signal buffering
- Low-power digital signal paths
- Mixed-mode signal operation
- Partial power-down systems
- Live insertion interfaces
- Back-drive protected logic nodes
- Compact board-level buffer placement
- Low-noise signal conditioning
Procurement Notes
When requesting a quote for SN74AUP1G34, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What logic function does the SN74AUP1G34 implement?
The SN74AUP1G34 implements a positive logic buffer function. Its datasheet logic relationship is Y = A, so the output follows the input within the specified operating and timing conditions.
What supply voltage range is recommended for this device?
The recommended operating supply voltage range is 0.8 V to 3.6 V. The input voltage range is 0 to 3.6 V, while the output voltage range is specified from 0 to VCC.
Which package options are listed for SN74AUP1G34?
The listed package options are SOT-5 1.60 mm x 1.20 mm, USON-6 1.45 mm x 1.00 mm, X2SON-4 0.80 mm x 0.80 mm, and DSBGA-4 0.79 mm x 0.79 mm.
Does SN74AUP1G34 support partial power-down operation?
Yes. Ioff support is listed for live insertion, partial power-down mode, and back-drive protection. The I/O pins are also specified as 3.6 V tolerant for mixed-mode signal operation.
What propagation delay is specified at 3.3 V?
At VCC = 3.3 V ±0.3 V and CL = 5 pF, A-to-Y propagation delay is 1.4 ns minimum, 2 ns typical, and 3.2 ns maximum at TA = 25°C, with 0.6 ns to 4.1 ns over temperature.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.