Specifications
| Type | Description |
|---|---|
| Part Number | SN74AUP2G34 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | SC70 (DCK) 6-pin; SON/QFN (DRY) 6-pin; SON/uQFN (DSF) 6-pin; DSBGA/NanoStar WCSP (YFP) 6-pin |
| Logic Function | Y = A; positive logic, dual non-inverting buffer |
| Supply Voltage Range | 0.8 to 3.6 V; recommended operating conditions |
| Operating Free-Air Temperature | -40 to 85 °C; recommended operating conditions |
| Input Voltage Range | 0 to 3.6 V; recommended operating conditions |
| Output Voltage Range | 0 to VCC; recommended operating conditions |
| High-Level Input Voltage | VCC; 0.65 x VCC; 1.6 V; 2 V at VCC=0.8 V; 1.1 to 1.95 V; 2.3 to 2.7 V; 3 to 3.6 V |
| Low-Level Input Voltage | 0 V; 0.35 x VCC; 0.7 V; 0.9 V at VCC=0.8 V; 1.1 to 1.95 V; 2.3 to 2.7 V; 3 to 3.6 V |
| High-Level Output Current | -20 mA; -1.1 mA; -1.7 mA; -1.9 mA; -3.1 mA; -4 mA at VCC=0.8 V; 1.1 V; 1.4 V; 1.65 V; 2.3 V; 3 V |
| Low-Level Output Current | 20 mA; 1.1 mA; 1.7 mA; 1.9 mA; 3.1 mA; 4 mA at VCC=0.8 V; 1.1 V; 1.4 V; 1.65 V; 2.3 V; 3 V |
| Input Transition Rise/Fall Rate | 200 ns/V max at VCC=0.8 to 3.6 V |
| Supply Voltage Absolute Maximum | -0.5 to 4.6 V |
| Input Voltage Absolute Maximum | -0.5 to 4.6 V |
| Output Voltage Absolute Maximum | -0.5 to VCC + 0.5 V; output in high or low state |
| Output Voltage High-Impedance or Power-Off Absolute Maximum | -0.5 to 4.6 V; applied to any output in high-impedance or power-off state |
| Input Clamp Current | -50 mA at VI < 0 |
| Output Clamp Current | -50 mA at VO < 0 |
| Continuous Output Current | ±20 mA; absolute maximum ratings |
| Continuous Current Through VCC or GND | ±50 mA; absolute maximum ratings |
| Storage Temperature Range | -65 to 150 °C; absolute maximum ratings |
| Package Thermal Impedance | DCK 252 °C/W; DRY 234 °C/W; DSF 300 °C/W; YFP 132 °C/W; junction-to-ambient per JESD51-7 |
| High-Level Output Voltage | VCC-0.1 V min; IOH=-20 mA, VCC=0.8 to 3.6 V, TA=-40 to 85 °C |
| Low-Level Output Voltage | 0.1 V max; IOL=20 mA, VCC=0.8 to 3.6 V, TA=-40 to 85 °C |
| Input Leakage Current | 0.1 µA typ, 0.5 µA max; A or B input, VI=GND to 3.6 V, VCC=0 to 3.6 V |
| Power-Off Leakage Current | 0.2 µA typ, 0.6 µA max; VI or VO=0 to 3.6 V, VCC=0 V |
| Delta Power-Off Leakage Current | 0.2 µA typ, 0.6 µA max; VI or VO=0 to 3.6 V, VCC=0 to 0.2 V |
| Supply Current | 0.5 µA typ, 0.9 µA max; VI=GND or VCC to 3.6 V, IO=0, VCC=0.8 to 3.6 V |
| Delta Supply Current | 40 µA typ, 50 µA max; VI=VCC-0.6 V, IO=0, VCC=3.3 V; one input at VCC-0.6 V, other at VCC or GND |
| Input Capacitance | 1.5 pF typ; VI=VCC or GND, VCC=0 V or 3.6 V |
| Output Capacitance | 3 pF typ; VO=GND, VCC=0 V |
| Propagation Delay, CL=5 pF | 2.4 ns typ, 3.5 ns max at TA=25°C; 0.5 to 4.3 ns over temperature; A or B to Y, VCC=3.3 V ±0.3 V |
| Propagation Delay, CL=10 pF | 2.9 ns typ, 4.2 ns max at TA=25°C; 0.5 to 4.7 ns over temperature; A or B to Y, VCC=3.3 V ±0.3 V |
| Propagation Delay, CL=15 pF | 3.4 ns typ, 4.8 ns max at TA=25°C; 0.5 to 5.9 ns over temperature; A or B to Y, VCC=3.3 V ±0.3 V |
| Propagation Delay, CL=30 pF | 4.7 ns typ, 6.2 ns max at TA=25°C; 1 to 7.5 ns over temperature; A or B to Y, VCC=3.3 V ±0.3 V |
| Power Dissipation Capacitance | 4 pF typ at 0.8 V, 1.2 V, 1.5 V, and 1.8 V; 4.1 pF typ at 2.5 V; 4.3 pF typ at 3.3 V; TA=25°C, f=10 MHz |
| Partial-Power-Down Support | Ioff circuitry disables outputs; prevents damaging current backflow when powered down |
| I/O Tolerance | 3.6 V tolerant; supports mixed-mode signal operation |
| ESD Human-Body Model | 2000 V; tested per JESD22 A114-B, Class II |
| ESD Charged-Device Model | 1000 V; tested per JESD22 C101 |
| Latch-Up Performance | Exceeds 100 mA; per JESD78, Class II |
| Datasheet Status | request_only |
Product Overview
The SN74AUP2G34 is a Texas Instruments low-power dual buffer gate for Signal_Chain use. Its logic function is Y = A, configured as a positive-logic dual non-inverting buffer. The recommended supply range is 0.8 to 3.6 V, with inputs specified from 0 to 3.6 V and outputs from 0 to VCC.
Electrical limits include -40 to 85 °C recommended free-air operation, 0.5 µA typical and 0.9 µA maximum supply current, and 1.5 pF typical input capacitance. At VCC = 3.3 V ±0.3 V and CL = 5 pF, propagation delay is 2.4 ns typical and 3.5 ns maximum at 25 °C.
Package options include 6-pin SC70 DCK, SON/QFN DRY, SON/uQFN DSF, and DSBGA/NanoStar WCSP YFP. The device supports 3.6 V tolerant I/O, mixed-mode signal operation, and partial-power-down use through Ioff circuitry that disables outputs to prevent damaging backflow current when powered down.
Key Features
- Positive-logic dual non-inverting buffer, Y = A
- 0.8 to 3.6 V recommended supply range
- 0 to 3.6 V recommended input voltage range
- 3.6 V tolerant I/O for mixed-mode operation
- Ioff circuitry disables outputs during power-down
- 0.5 µA typical supply current at specified conditions
- 1.5 pF typical input capacitance
- Propagation delay specified from 5 pF to 30 pF loads
- 2000 V HBM and 1000 V CDM ESD ratings
- 6-pin SC70, SON/QFN, SON/uQFN, and WCSP options
Typical Applications
- Mixed-mode signal buffering
- Low-voltage logic buffering
- Power-down protected signal paths
- Compact 6-pin logic designs
- Battery-powered signal chain interfaces
- Input-to-output non-inverting logic paths
Procurement Notes
When requesting a quote for SN74AUP2G34, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What logic function does the SN74AUP2G34 provide?
The SN74AUP2G34 provides a positive-logic dual non-inverting buffer function. The extracted logic relationship is Y = A, so each output follows its corresponding input within the specified operating conditions.
What supply voltage range is recommended for SN74AUP2G34?
The recommended supply voltage range is 0.8 to 3.6 V. The device also specifies a 0 to 3.6 V input voltage range and an output voltage range from 0 to VCC under recommended operating conditions.
Which package options are listed for this device?
The listed 6-pin package options are SC70 DCK, SON/QFN DRY, SON/uQFN DSF, and DSBGA/NanoStar WCSP YFP. Package thermal impedance values are specified separately for DCK, DRY, DSF, and YFP.
Does SN74AUP2G34 support power-off protection behavior?
Yes. The extracted facts list partial-power-down support using Ioff circuitry that disables outputs. This behavior is specified to prevent damaging current backflow when the device is powered down.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.