SN74LVC1G14 Single Schmitt-Trigger Inverter

Texas Instruments Signal_Chain — specifications, applications, sourcing support and RFQ.

SN74LVC1G14 Single Schmitt-Trigger Inverter

RFQ Available Sourcing Support Alternative Matching RoHS
Part Number
SN74LVC1G14
Manufacturer
Texas Instruments
Package
DBV SOT-23-5 2.90mm x 1.60mm body; DCK SC70-5 2.00mm x 1.25mm body; DRL SOT-5X3-5 1.60mm x 1.20mm body; DRY USON-6 1.45mm x 1.00mm body; DSF X2SON-6 1.00mm x 1.00mm body; YZP DSBGA-5 1.39mm x 0.89mm body; YZV DSBGA-4 0.89mm x 0.89mm body; DPW X2SON-5 0.80mm x 0.80mm body
Category
Signal Chain
Product Type
Operational Amplifier

Quick Sourcing Note

SN74LVC1G14 from Texas Instruments is a Signal_Chain single Schmitt-trigger inverter with positive-logic function Y = NOT A. It operates from a 1.65 V to 5.5 V supply, supports 0 V to 5.5 V input voltage, and provides an output range from 0 V to VCC. Package options include SOT-23-5, SC70-5, SOT-5X3-5, USON-6, X2SON, and DSBGA body sizes. Key parameters include Schmitt-trigger thresholds, input hysteresis, low input capacitance, power-off leakage support, Ioff partial-power-down circuitry, and propagation delay ratings across 1.8 V, 2.5 V, 3.3 V, and 5 V operation.

Specifications

TypeDescription
Part NumberSN74LVC1G14
ManufacturerTexas Instruments
Product TypeOperational Amplifier
CategorySignal Chain
Component TypeOther
Package / CaseDBV SOT-23-5 2.90mm x 1.60mm body; DCK SC70-5 2.00mm x 1.25mm body; DRL SOT-5X3-5 1.60mm x 1.20mm body; DRY USON-6 1.45mm x 1.00mm body; DSF X2SON-6 1.00mm x 1.00mm body; YZP DSBGA-5 1.39mm x 0.89mm body; YZV DSBGA-4 0.89mm x 0.89mm body; DPW X2SON-5 0.80mm x 0.80mm body
Logic FunctionY = NOT A
Supply Voltage Range1.65 V to 5.5 V
Data Retention Supply Voltage1.5 V
Input Voltage Range0 V to 5.5 V
Output Voltage Range0 V to VCC
Absolute Maximum Supply Voltage-0.5 V to 6.5 V
Absolute Maximum Input Voltage-0.5 V to 6.5 V
Absolute Maximum Output Voltage-0.5 V to 6.5 V
Absolute Maximum Output Voltage-0.5 V to VCC + 0.5 V
Input Clamp Current-50 mA
Output Clamp Current-50 mA
Continuous Output Current+/-50 mA
Continuous Current Through VCC or GND+/-100 mA
Maximum Junction Temperature150 °C
Storage Temperature-65 °C to 150 °C
ESD HBM Rating2000 V
ESD CDM Rating1000 V
ESD Machine Model Rating200 V
High-Level Output Current-4 mA, -8 mA, -16 mA, -24 mA, -32 mA
Low-Level Output Current4 mA, 8 mA, 16 mA, 24 mA, 32 mA
Operating Free-Air Temperature-40 °C to 85 °C
Operating Free-Air Temperature-40 °C to 125 °C
Positive-Going Input Threshold Voltage VT+min 0.79 V, max 1.16 V
Positive-Going Input Threshold Voltage VT+min 1.11 V, max 1.56 V
Positive-Going Input Threshold Voltage VT+min 1.5 V, max 1.87 V
Positive-Going Input Threshold Voltage VT+min 2.16 V, max 2.74 V
Positive-Going Input Threshold Voltage VT+min 2.61 V, max 3.33 V
Negative-Going Input Threshold Voltage VT-min 0.39 V, max 0.62 V at -40 °C to 85 °C; min 0.39 V, max 0.64 V at -40 °C to 125 °C
Negative-Going Input Threshold Voltage VT-min 0.58 V, max 0.87 V at -40 °C to 85 °C; min 0.58 V, max 0.89 V at -40 °C to 125 °C
Negative-Going Input Threshold Voltage VT-min 0.84 V, max 1.14 V at -40 °C to 85 °C; min 0.84 V, max 1.16 V at -40 °C to 125 °C
Negative-Going Input Threshold Voltage VT-min 1.41 V, max 1.79 V
Negative-Going Input Threshold Voltage VT-min 1.87 V, max 2.29 V
Negative-Going Input Threshold Voltage VT-min 0.44 V, max 0.67 V; min 0.63 V, max 0.92 V; min 0.89 V, max 1.19 V; min 1.46 V, max 1.84 V; min 1.92 V, max 2.34 V
Input Hysteresis ΔVTmin 0.37 V, max 0.62 V; min 0.48 V, max 0.77 V; min 0.56 V, max 0.87 V; min 0.71 V, max 1.04 V; min 0.71 V, max 1.11 V
High-Level Output Voltage VOHmin VCC - 0.1 V
High-Level Output Voltage VOHmin 1.2 V, 1.9 V, 2.4 V, 2.3 V, 3.8 V
Low-Level Output Voltage VOLmax 0.1 V
Low-Level Output Voltage VOLmax 0.45 V, 0.3 V, 0.4 V, 0.55 V, 0.55 V at -40 °C to 85 °C; max 0.45 V, 0.3 V, 0.4 V, 0.55 V, 0.7 V at -40 °C to 125 °C
Input Leakage Current IImax +/-5 µA
Power-Off Leakage Current Ioffmax +/-10 µA
Supply Current ICCmax 10 µA
Delta Supply Current ΔICCmax 500 µA
Input Capacitance Cityp 4.5 pF
Propagation Delay tpdmin 2.8 ns, max 9.9 ns with CL=15 pF; min 3.8 ns, max 11 ns with CL=30 pF
Propagation Delay tpdmin 1.6 ns, max 5.5 ns with CL=15 pF; min 2 ns, max 6.5 ns with CL=30 pF
Propagation Delay tpdmin 1.5 ns, max 4.6 ns with CL=15 pF; min 1.8 ns, max 5.5 ns with CL=50 pF
Propagation Delay tpdmin 0.9 ns, max 4.4 ns with CL=15 pF; min 1.2 ns, max 5 ns with CL=50 pF
Propagation Delay tpdmin 3.8 ns, max 13 ns; min 2 ns, max 8 ns; min 1.8 ns, max 6.5 ns; min 1.2 ns, max 6 ns
Power Dissipation Capacitance Cpdtyp 20 pF, 21 pF, 22 pF, 25 pF
Latch-Up PerformanceExceeds 100 mA
Partial-Power-Down SupportIoff circuitry disables outputs when powered down
Datasheet Statusrequest_only

Product Overview

The SN74LVC1G14 is a Texas Instruments single Schmitt-trigger inverter in the Signal_Chain category. Its positive-logic function is Y = NOT A, using a Schmitt-trigger input stage with specified positive-going and negative-going input thresholds plus hysteresis across supply voltages from 1.65 V to 5.5 V.

Recommended operating conditions specify a 1.65 V to 5.5 V supply range, 1.5 V data-retention supply voltage, 0 V to 5.5 V input range, and 0 V to VCC output range. Output drive ratings are specified up to -32 mA high-level current and 32 mA low-level current at the listed VCC conditions, with leakage, supply current, input capacitance, and propagation delay characterized in the datasheet facts.

Assembly options include DBV SOT-23-5, DCK SC70-5, DRL SOT-5X3-5, DRY USON-6, DSF X2SON-6, YZP DSBGA-5, YZV DSBGA-4, and DPW X2SON-5 packages. Applications should align with single-gate inversion, Schmitt-trigger input conditioning, low-voltage logic interfacing, and partial-power-down signal paths using Ioff circuitry.

Key Features

  • Single Schmitt-trigger inverter with Y = NOT A logic
  • 1.65 V to 5.5 V recommended supply range
  • 0 V to 5.5 V recommended input voltage range
  • 1.5 V supply condition for data retention only
  • Input hysteresis specified across 1.65 V to 5.5 V
  • Propagation delay characterized from 1.8 V to 5 V
  • Ioff circuitry disables outputs during power-down
  • Typical input capacitance is 4.5 pF at 3.3 V
  • Latch-up performance exceeds 100 mA per JESD 78
  • Multiple SOT, SC70, USON, X2SON, and DSBGA packages

Typical Applications

  • Single-gate logic inversion
  • Schmitt-trigger input conditioning
  • Low-voltage logic signal paths
  • Partial-power-down interfaces
  • Compact board-level logic
  • Data-retention logic circuits
  • Threshold-based digital input cleanup

Procurement Notes

When requesting a quote for SN74LVC1G14, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.

If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.

For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.

FAQ

What logic function does the SN74LVC1G14 provide?

The SN74LVC1G14 provides a positive-logic inverter function, specified as Y = NOT A. The input uses a Schmitt-trigger structure, with positive-going and negative-going threshold voltages characterized across the listed supply voltages.

What supply range is specified for normal operation?

The recommended operating supply range is 1.65 V to 5.5 V. The extracted facts also specify a 1.5 V supply condition for data retention only, separate from the normal recommended operating range.

Which package options are listed for this device?

The listed packages include DBV SOT-23-5, DCK SC70-5, DRL SOT-5X3-5, DRY USON-6, DSF X2SON-6, YZP DSBGA-5, YZV DSBGA-4, and DPW X2SON-5 body sizes.

Does the SN74LVC1G14 support partial-power-down operation?

Yes. The extracted facts state that Ioff circuitry disables outputs when the device is powered down, preventing current backflow into the device under the specified partial-power-down support condition.

Technical Review & Sourcing Note

Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.

This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.

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