Specifications
| Type | Description |
|---|---|
| Part Number | SN75LVDS83 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 56-pin TSSOP DGG 14.00 mm x 5.10 mm; 56-ball BGA MICROSTAR JUNIOR ZQL 7.00 mm x 4.50 mm |
| Component Type | Other |
| Function | 28-bit LVTTL parallel input to 4 LVDS serial data channels plus LVDS clock; FlatLink transmitter architecture |
| Pixel Clock Frequency Range | 10-135 MHz; CLKIN input clock |
| Transfer Rate | Up to 135 Mpps; Mega pixels per second |
| Supply Voltage | 3.3 V single supply; normal operation |
| Typical Power Consumption | 170 mW; 75 MHz operation |
| Disabled Power Consumption | Less than 1 mW; device disabled |
| Input Voltage Compatibility | 1.8 V to 3.3 V tolerant data inputs; connects directly to low-power application and graphics processors |
| Clock Edge Selection | Selectable rising or falling edge triggered inputs; CLKSEL high selects rising edge, CLKSEL low selects falling edge |
| Clock Multiplication | 7x; CLKIN frequency multiplied by internal clock synthesizer |
| LVDS Clock Output Frequency | Same as CLKIN; CLKOUT phase-locked clock output |
| ESD Rating | 5 kV HBM; Human Body Model |
| Spread Spectrum Clocking | Supported; SSC support feature |
| Operating Free-Air Temperature | -10 to 70 °C; characterized operation |
| Absolute Maximum Supply Voltage Range | -0.5 to 4 V; VCC, IOVCC, LVDSVCC, PLLVCC with respect to GND |
| Absolute Maximum Output Terminal Voltage | -0.5 to VCC + 0.5 V; any output terminal |
| Absolute Maximum Input Terminal Voltage | -0.5 to IOVCC + 0.5 V; any input terminal |
| Storage Temperature Range | -65 to 150 °C; handling rating |
| ESD Rating HBM | 5 kV; all pins, JEDEC 22 A114-A |
| ESD Rating CDM | 500 V; all pins, JEDEC 22 C101 |
| ESD Rating MM | 150 V; all pins, JEDEC 22 A115-A |
| Recommended VCC | 3.0 V min, 3.3 V nom, 3.6 V max; recommended operating conditions |
| Recommended LVDSVCC | 3.0 V min, 3.3 V nom, 3.6 V max; LVDS output supply voltage |
| Recommended PLLVCC | 3.0 V min, 3.3 V nom, 3.6 V max; PLL analog supply voltage |
| Recommended IOVCC | 1.62 V min, 1.8/2.5/3.3 V nom, 3.6 V max; I/O input reference supply voltage |
| Power Supply Noise | 0.1 V max; any VCC terminal |
| High-Level Input Voltage at 1.8 V IOVCC | IOVCC/2 + 0.3 V |
| High-Level Input Voltage at 2.5 V IOVCC | IOVCC/2 + 0.4 V |
| High-Level Input Voltage at 3.3 V IOVCC | IOVCC/2 + 0.5 V |
| Low-Level Input Voltage at 1.8 V IOVCC | IOVCC/2 - 0.3 V |
| Low-Level Input Voltage at 2.5 V IOVCC | IOVCC/2 - 0.4 V |
| Low-Level Input Voltage at 3.3 V IOVCC | IOVCC/2 - 0.5 V |
| Differential Load Impedance | 90-132 ohm; LVDS differential load |
| Shutdown Input Behavior | Active low; inhibits clock, shuts off LVDS output drivers, clears internal registers low; SHTDN low |
| LVDS Output State in Shutdown | High impedance; SHTDN pulled low |
| Alternative Device Option | SN75LVDS83A; alternative for 10-100 MHz clock frequency range, TSSOP package only |
| Datasheet Status | request_only |
Product Overview
The SN75LVDS83 is a Texas Instruments LVDS FlatLink transmitter in the Signal_Chain category. Its FlatLink architecture accepts a 28-bit LVTTL parallel input and outputs four LVDS serial data channels plus a phase-locked LVDS clock output. The LVDS clock output frequency is the same as CLKIN, while the internal clock synthesizer multiplies CLKIN by 7x.
The device supports a 10-135 MHz CLKIN pixel clock frequency range and transfer rates up to 135 Mpps. It operates from a 3.3 V single supply, with recommended VCC, LVDSVCC, and PLLVCC ranges of 3.0 V to 3.6 V. IOVCC supports 1.62 V minimum and 1.8 V, 2.5 V, or 3.3 V nominal references for tolerant data inputs.
Package options include 56-pin TSSOP DGG at 14.00 mm x 5.10 mm and 56-ball BGA MICROSTAR JUNIOR ZQL at 7.00 mm x 4.50 mm. The active-low shutdown input inhibits the clock, shuts off LVDS drivers, clears internal registers low, and places LVDS outputs in high impedance.
Key Features
- 28-bit LVTTL input to four LVDS data channels
- LVDS clock output provided with FlatLink transmitter architecture
- CLKIN pixel clock range from 10 MHz to 135 MHz
- Transfer rate supports up to 135 Mpps
- Operates from a 3.3 V single supply
- Typical 170 mW power consumption at 75 MHz
- Disabled power consumption is less than 1 mW
- Data inputs tolerate 1.8 V to 3.3 V
- Selectable rising or falling input clock edge
- Spread spectrum clocking is supported
Typical Applications
- Low-power application processor links
- Graphics processor LVDS outputs
- FlatLink transmitter interfaces
- 28-bit LVTTL to LVDS conversion
- 135 Mpps display data transfer
- Spread spectrum clocked LVDS links
Procurement Notes
When requesting a quote for SN75LVDS83, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What function does the SN75LVDS83 perform?
The SN75LVDS83 is a Texas Instruments LVDS FlatLink transmitter that converts a 28-bit LVTTL parallel input into four LVDS serial data channels plus an LVDS clock output.
What CLKIN frequency range does SN75LVDS83 support?
The CLKIN pixel clock frequency range is 10-135 MHz. The internal clock synthesizer multiplies CLKIN by 7x, and the LVDS clock output frequency is the same as CLKIN.
What supply voltages are recommended for this transmitter?
Recommended VCC, LVDSVCC, and PLLVCC are each 3.0 V minimum, 3.3 V nominal, and 3.6 V maximum. Recommended IOVCC is 1.62 V minimum with 1.8 V, 2.5 V, or 3.3 V nominal operation.
What happens when SHTDN is pulled low?
SHTDN is active low. When pulled low, it inhibits the clock, shuts off the LVDS output drivers, clears internal registers low, and places the LVDS outputs in a high-impedance state.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.