Specifications
| Type | Description |
|---|---|
| Part Number | SN75LVDS83B |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | TSSOP-56 DGG, 14.00 mm x 5.10 mm nominal body; BGA MICROSTAR JUNIOR-56 ZQL, 7.00 mm x 4.50 mm nominal body |
| Function | 28-bit LVTTL-to-LVDS FlatLink transmitter; 4 serial LVDS data channels plus LVDS clock output |
| Input Data Channels | 28; D0 through D27 single-ended LVTTL inputs |
| LVDS Data Outputs | 4 differential data channels; Y0, Y1, Y2, Y3 LVDS outputs |
| LVDS Clock Outputs | 1 differential clock channel; CLKOUT / CLKP, CLKM output |
| Pixel Transfer Rate | Up to 135 Mpps; Mega pixels per second |
| Pixel Clock Frequency Range | 10 MHz to 135 MHz; CLKIN operating frequency |
| Typical Power Consumption | 170 mW at 75 MHz operation |
| Disabled Power Consumption | Less than 1 mW when device is disabled by SHTDN |
| ESD Rating, HBM | 5 kV Human Body Model |
| Clock Edge Selection | Rising or falling edge selectable; CLKSEL high selects rising edge, CLKSEL low selects falling edge |
| Shutdown Input | Active low; SHTDN low shuts down device, inhibits clock, disables LVDS outputs, and clears internal registers |
| Operating Free-Air Temperature | -10 to 70 °C recommended operating condition |
| Supply Voltage | 3.0 V min, 3.3 V nom, 3.6 V max; VCC recommended operating condition |
| LVDS Output Supply Voltage | 3.0 V min, 3.3 V nom, 3.6 V max; LVDSVCC recommended operating condition |
| PLL Analog Supply Voltage | 3.0 V min, 3.3 V nom, 3.6 V max; PLLVCC recommended operating condition |
| I/O Reference Supply Voltage | 1.62 V min, 1.8/2.5/3.3 V nom, 3.6 V max; IOVCC recommended operating condition |
| Power Supply Noise | 0.1 V max at any VCC terminal |
| High-Level Input Voltage, IOVCC = 1.8 V | IOVCC/2 + 0.3 V |
| High-Level Input Voltage, IOVCC = 2.5 V | IOVCC/2 + 0.4 V |
| High-Level Input Voltage, IOVCC = 3.3 V | IOVCC/2 + 0.5 V |
| Low-Level Input Voltage, IOVCC = 1.8 V | IOVCC/2 - 0.3 V |
| Low-Level Input Voltage, IOVCC = 2.5 V | IOVCC/2 - 0.4 V |
| Low-Level Input Voltage, IOVCC = 3.3 V | IOVCC/2 - 0.5 V |
| Differential Load Impedance | 90 to 132 ohm; ZL recommended operating condition |
| Absolute Maximum Supply Voltage Range | -0.5 to 4 V; VCC, IOVCC, LVDSVCC, PLLVCC with respect to GND |
| Absolute Maximum Output Terminal Voltage | -0.5 V to VCC + 0.5 V; any output terminal |
| Absolute Maximum Input Terminal Voltage | -0.5 V to IOVCC + 0.5 V; any input terminal |
| Storage Temperature Range | -65 to 150 °C handling rating |
| ESD Rating, HBM All Pins | 5 kV Human Body Model, all pins, JEDEC 22 A114-A |
| ESD Rating, CDM All Pins | 500 V Charged Device Model, all pins, JEDEC 22 C101 |
| ESD Rating, MM All Pins | 150 V Machine Model, all pins, JEDEC 22 A115-A |
| Datasheet Status | request_only |
Product Overview
The SN75LVDS83B is a Texas Instruments FlatLink LVDS transmitter in the Signal_Chain category. Its function is 28-bit LVTTL-to-LVDS conversion, using D0 through D27 as single-ended LVTTL inputs and serializing data onto four differential LVDS data channels. A separate differential LVDS clock output is provided on CLKOUT / CLKP and CLKM.
The transmitter supports a pixel transfer rate up to 135 Mpps and operates from a 10 MHz to 135 MHz CLKIN frequency range. At 75 MHz operation, typical power consumption is 170 mW. When SHTDN is driven low, the device shuts down, inhibits the clock, disables LVDS outputs, and clears internal registers, reducing disabled power consumption to less than 1 mW.
Supply domains include VCC, LVDSVCC, and PLLVCC at 3.0 V to 3.6 V, with IOVCC supporting 1.62 V to 3.6 V and nominal 1.8 V, 2.5 V, or 3.3 V operation. Package options are TSSOP-56 DGG and BGA MICROSTAR JUNIOR-56 ZQL.
Key Features
- 28-bit LVTTL-to-LVDS FlatLink transmitter function
- D0 through D27 single-ended LVTTL input channels
- Four differential LVDS data outputs: Y0 through Y3
- One differential LVDS clock output channel
- Supports up to 135 Mpps pixel transfer rate
- 10 MHz to 135 MHz CLKIN operating range
- 170 mW typical power consumption at 75 MHz
- Less than 1 mW disabled power via SHTDN
- Selectable rising or falling clock edge capture
- 3.0 V to 3.6 V VCC operating range
- 1.62 V to 3.6 V IOVCC range
- -10 to 70 °C free-air operation
Typical Applications
- LVTTL-to-LVDS data transmission
- FlatLink display interface transmitters
- 28-bit parallel input serialization
- Four-channel LVDS data links
- 135 Mpps pixel data paths
- Selectable-edge clocked interfaces
- Low-power shutdown signal paths
Procurement Notes
When requesting a quote for SN75LVDS83B, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What function does the SN75LVDS83B perform?
The SN75LVDS83B is a 28-bit LVTTL-to-LVDS FlatLink transmitter. It accepts D0 through D27 single-ended LVTTL inputs and drives four serial LVDS differential data channels plus one differential LVDS clock output.
What clock range does the SN75LVDS83B support?
The CLKIN operating frequency range is 10 MHz to 135 MHz. The device supports a pixel transfer rate up to 135 Mpps, specified as mega pixels per second.
How does the SHTDN input affect the device?
SHTDN is an active-low shutdown input. When SHTDN is low, the device shuts down, inhibits the clock, disables the LVDS outputs, and clears internal registers. Disabled power consumption is less than 1 mW.
What supply voltages are specified for SN75LVDS83B operation?
VCC, LVDSVCC, and PLLVCC each have recommended operating conditions of 3.0 V minimum, 3.3 V nominal, and 3.6 V maximum. IOVCC supports 1.62 V minimum, nominal 1.8 V, 2.5 V, or 3.3 V, and 3.6 V maximum.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.