Specifications
| Type | Description |
|---|---|
| Part Number | TMDS181 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 48-pin VQFN (RGZ), 7.00 mm x 7.00 mm body, 0.5 mm pitch |
| Interface Type | Digital video interface (DVI) / HDMI retimer |
| Maximum TMDS Data Rate | 6 Gbps |
| Supported Channels | 4 TMDS channels |
| Channel Arrangement | Three data channels plus clock channel |
| HDMI Electrical Compatibility | Compatible with HDMI electrical parameters up to 6 Gbps |
| Supported Video Resolution | 4k2k60p, 24 bits per pixel |
| Supported Color Depth / Resolution | Up to WUXGA 16-bit color depth |
| Supported HDMI Standard Configuration | HDMI 2.0a |
| Low Data Rate Mode | Redriver mode automatically selected below 1.0 Gbps |
| Redriver Mode Maximum Data Rate | 3.4 Gbps for HDMI 1.4b support |
| Retimer Function | Retimes input stream to compensate for random jitter |
| Inter-Pair Skew Compensation | 5+ bits |
| Receiver Equalization | Adaptive receiver equalizer or programmable fixed equalizer |
| Equalization Control | Controlled by I2C or pin strap |
| Fixed EQ Pin-Strap Setting | 7.5 dB at 3 GHz when EQ_SEL = Low and I2C_EN/PIN = Low |
| Adaptive EQ Pin-Strap Setting | Adaptive EQ when EQ_SEL = No Connect and I2C_EN/PIN = Low |
| High Fixed EQ Pin-Strap Setting | 14 dB at 3 GHz when EQ_SEL = High and I2C_EN/PIN = Low |
| De-Emphasis Pin-Strap Setting, Low | -2 dB when PRE_SEL = Low and I2C_EN/PIN = Low |
| De-Emphasis Pin-Strap Setting, No Connect | 0 dB when PRE_SEL = No Connect and I2C_EN/PIN = Low |
| VDD Power Supply Voltage | 1.2 V |
| VCC Power Supply Voltage | 3.3 V |
| Audio Return Channel Support | Single-ended mode ARC support |
| ARC Interface | SPDIF_IN / ARC_OUT interface |
| DDC Interface | Source-side and sink-side bidirectional DDC data and clock lines |
| DDC Pins | SDA_SRC, SCL_SRC, SDA_SNK, SCL_SNK |
| Control Interface | I2C and pin-strap programmable |
| Operation Enable Function | OE = Low: power-down mode; OE = High: normal operation |
| Signal Detect Function | When SIG_EN = High and no valid clock is present, device enters standby mode |
| Commercial Operating Temperature | 0°C to 85°C for TMDS181 |
| Industrial Operating Temperature | -40°C to 85°C for TMDS181I |
| Datasheet Status | request_only |
Product Overview
The TMDS181 is a Texas Instruments 6 Gbps TMDS retimer for DVI and HDMI digital video interfaces. It handles four TMDS channels, organized as three data channels plus one clock channel, and retimes the main TMDS data stream to compensate for random jitter. In retimer mode, it supports HDMI electrical parameters up to 6 Gbps.
For video links, the device supports 4k2k60p at 24 bits per pixel at signaling rates up to 6 Gbps. It also supports up to WUXGA with 16-bit color depth and can be configured to support HDMI 2.0a. Below 1.0 Gbps, the device automatically selects redriver mode; for HDMI 1.4b support, redriver mode operates up to 3.4 Gbps.
Configuration is available through I2C or pin straps. Receiver equalization can be adaptive or fixed, with pin-strap settings for 7.5 dB or 14 dB at 3 GHz, and de-emphasis settings of -2 dB or 0 dB. The 48-pin VQFN (RGZ) package has a 7.00 mm x 7.00 mm body with 0.5 mm pitch.
Key Features
- 6 Gbps TMDS retimer for DVI and HDMI interfaces
- Four TMDS channels: three data channels plus clock
- Supports HDMI electrical parameters up to 6 Gbps
- Supports 4k2k60p video at 24 bits per pixel
- Configurable for HDMI 2.0a standard operation
- Automatically selects redriver mode below 1.0 Gbps
- Redriver mode supports HDMI 1.4b up to 3.4 Gbps
- Retimes TMDS stream to compensate for random jitter
- Provides 5+ bits inter-pair skew compensation
- Adaptive or programmable fixed receiver equalization
- I2C and pin-strap programmable device configuration
- Single-ended ARC support through SPDIF_IN and ARC_OUT
Typical Applications
- DVI video interface retiming
- HDMI video interface retiming
- 4k2k60p video links
- HDMI 2.0a signal paths
- HDMI 1.4b redriver links
- TMDS jitter compensation
- TMDS inter-pair skew compensation
- DDC source-to-sink communication
- ARC single-ended audio return
Procurement Notes
When requesting a quote for TMDS181, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What interface does the TMDS181 support?
The TMDS181 is specified as a digital video interface retimer for DVI and HDMI. It supports four TMDS channels, consisting of three data channels and one clock channel.
What is the maximum TMDS data rate of TMDS181?
In retimer mode, the TMDS181 supports a maximum TMDS data rate of 6 Gbps and is compatible with HDMI electrical parameters up to 6 Gbps.
How is receiver equalization configured on TMDS181?
Receiver equalization can be set as adaptive equalization or programmable fixed equalization. Configuration is available through I2C or pin straps, including fixed settings of 7.5 dB and 14 dB at 3 GHz.
What package is used for the TMDS181?
The TMDS181 is provided in a 48-pin VQFN (RGZ) package. The package body is 7.00 mm x 7.00 mm with 0.5 mm pitch.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.