Specifications
| Type | Description |
|---|---|
| Part Number | TS3DDR4000 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 48-ball NFBGA ZBA, 8.00 mm x 3.00 mm, 0.65 mm pitch |
| Bus width | 12-bit; A port switched to B or C for all bits simultaneously |
| Switch topology | 1:2 or 2:1; high-speed DDR2/DDR3/DDR4 switch/multiplexer |
| Supported signaling standards | POD_12, SSTL_12, SSTL_15, SSTL_18 for DDR memory bus signaling |
| Supply voltage range | 2.375 to 3.6 V; recommended operating conditions, VDD |
| Absolute maximum VDD voltage range | -0.3 to 4.8 V; absolute maximum ratings |
| Control input absolute maximum voltage range | -0.3 to 5.5 V; SEL0, SEL1, and /EN |
| Analog I/O absolute maximum voltage range | -0.3 to 3.6 V; A0-A11, B0-B11, C0-C11 |
| Recommended analog I/O voltage range | 0 to 3.3 V; A0-A11, B0-B11, C0-C11 |
| Operating ambient temperature | -40 to 85 °C; recommended operating conditions |
| Storage temperature | -65 to 125 °C; absolute maximum ratings |
| EN high-level input threshold | 1.4 V to VDD; recommended operating conditions |
| SEL0/SEL1 high-level input threshold | 1 V to VDD; recommended operating conditions |
| Control low-level input threshold | 0 to 0.5 V; EN, SEL0, SEL1 |
| Human body model ESD rating | ±3000 V; all pins, JEDEC A114 |
| Charged device model ESD rating | ±1000 V; JEDEC C101 |
| Junction-to-ambient thermal resistance | 92.6 °C/W; 48-ball BGA package |
| Junction-to-case top thermal resistance | 33.4 °C/W; 48-ball BGA package |
| Junction-to-board thermal resistance | 56.2 °C/W; 48-ball BGA package |
| Junction-to-top characterization parameter | 1.3 °C/W; 48-ball BGA package |
| Junction-to-board characterization parameter | 54.9 °C/W; 48-ball BGA package |
| On-state resistance, Port A to B | 8.3 typ, 11.2 max Ω; VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| On-state resistance, Port A to C | 8.3 typ, 11.2 max Ω; VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| On-state resistance flatness | 0.6 typ Ω; Port A to B or A to C, VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| On-state resistance channel match | 0.2 typ, 1.0 max Ω; Port A to B or A to C, VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| Control input high leakage current | ±1 max µA; EN/SEL inputs, VDD=3.6 V with input=1.4 V or VDD=2.375 V with input=3.3 V |
| Control input low leakage current | ±0.5 max µA; EN/SEL inputs, VDD=3.6 V, input=0 V |
| Power-off leakage current | ±5 max µA; VDD=0 V, VI/O=0 to 3.3 V, control input=0 V or 3.6 V |
| VDD supply current, select inputs 0 V | 28 typ, 35 max µA; VDD=3.6 V, II/O=0 A, /EN=0 V |
| VDD supply current, select inputs 1.8 V | 40 typ, 48 max µA; VDD=3.6 V, II/O=0 A, /EN=0 V |
| Power-down supply current | 2 typ, 5 max µA; VDD=3.6 V, II/O=0 A, /EN=1.8 V |
| Switch turn-on time | 65 typ, 140 max µs; EN to B or C, VDD=2.375 V, RL=50 Ω, VAn=3.3 V |
| Channel switching time to B | 65 typ ns; SEL to B, VDD=2.375 V, /EN=0 V, RL=50 Ω, VAn=3.3 V |
| Channel switching time to C | 50 typ ns; SEL to C, VDD=2.375 V, /EN=0 V, RL=50 Ω, VAn=3.3 V |
| Propagation delay | 85 typ ps; Port A to B or Port A to C, VDD=2.375 V |
| Single-ended skew between channels | 3 typ, 8 max ps for B outputs; 3 typ, 6 max ps for C outputs; VDD=2.375 V |
| Control input capacitance | 6 typ pF; EN, SEL1, SEL2; f=1 MHz, VIN=0 V |
| Switch off capacitance | 0.5 typ pF; Port A to B or A to C, f=1067 MHz, VI/O=0 V |
| Switch on capacitance | 1.0 typ pF; Port A to B or A to C, f=1067 MHz, VI/O=1.2 V |
| Crosstalk between channels | -34 typ dB for B0 to B11; -31 typ dB for C0 to C11; f=1067 MHz, RL=50 Ω |
| Off isolation | -21 typ dB; Port A to B or A to C, f=1067 MHz, RL=50 Ω |
| Insertion loss | -0.75 typ, -1 max dB; Port A to B or A to C, f=DC, RL=50 Ω |
| Single-ended -3 dB bandwidth | 5.6 typ GHz; Port A to B or A to C, RL=50 Ω |
| Differential -3 dB bandwidth | 6 typ GHz; Port A to B or A to C, RL=100 Ω |
| Datasheet Status | request_only |
Product Overview
The Texas Instruments TS3DDR4000 is a 12-bit DDR switch multiplexer for Signal_Chain designs using DDR memory bus signaling. Its topology supports 1:2 or 2:1 switching, with the A port switched to B or C for all bits simultaneously. Supported signaling standards include POD_12, SSTL_12, SSTL_15, and SSTL_18.
The device operates from a recommended VDD range of 2.375 to 3.6 V and supports a recommended analog I/O voltage range of 0 to 3.3 V across A0-A11, B0-B11, and C0-C11. Control thresholds include 1.4 V to VDD for EN high level, 1 V to VDD for SEL0/SEL1 high level, and 0 to 0.5 V for low-level control inputs.
TS3DDR4000 is packaged in a 48-ball NFBGA ZBA measuring 8.00 mm x 3.00 mm with 0.65 mm pitch. Electrical characteristics include 8.3 Ω typical on-state resistance, 85 ps typical propagation delay, 5.6 GHz typical single-ended bandwidth, and 6 GHz typical differential bandwidth for A-to-B or A-to-C paths.
Key Features
- 12-bit A-to-B or A-to-C simultaneous bus switching
- 1:2 or 2:1 DDR switch multiplexer topology
- Supports POD_12, SSTL_12, SSTL_15, and SSTL_18 signaling
- 2.375 to 3.6 V recommended VDD operating range
- 0 to 3.3 V recommended analog I/O range
- 8.3 Ω typical on-state resistance per selected path
- 85 ps typical propagation delay from A to B or C
- 5.6 GHz typical single-ended -3 dB bandwidth
- 6 GHz typical differential -3 dB bandwidth
- 48-ball NFBGA package with 0.65 mm pitch
Typical Applications
- DDR2 memory bus switching
- DDR3 memory bus multiplexing
- DDR4 memory bus switching
- POD_12 signaling paths
- SSTL_12 signal routing
- SSTL_15 signal routing
- SSTL_18 signal routing
- 12-bit bus selection
Procurement Notes
When requesting a quote for TS3DDR4000, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the TS3DDR4000?
The TS3DDR4000 is a Texas Instruments 12-bit DDR switch multiplexer in the Signal_Chain category. It supports 1:2 or 2:1 switching and switches the A port to either B or C for all 12 bits simultaneously.
What supply voltage range does TS3DDR4000 support?
The recommended VDD operating range for TS3DDR4000 is 2.375 to 3.6 V. Its absolute maximum VDD voltage range is -0.3 to 4.8 V, according to the extracted datasheet ratings.
Which DDR signaling standards are listed for this part?
The extracted facts list POD_12, SSTL_12, SSTL_15, and SSTL_18 as supported signaling standards for DDR memory bus signaling. These standards apply to the device's DDR bus switch and multiplexer function.
What package is used for the TS3DDR4000?
TS3DDR4000 is supplied in a 48-ball NFBGA ZBA package. The package dimensions are 8.00 mm x 3.00 mm with a 0.65 mm ball pitch.
What are the main high-speed parameters for TS3DDR4000?
Key high-speed parameters include 85 ps typical propagation delay, 5.6 GHz typical single-ended -3 dB bandwidth, 6 GHz typical differential -3 dB bandwidth, and 0.5 pF typical switch off capacitance at 1067 MHz.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.