Specifications
| Type | Description |
|---|---|
| Part Number | TS3DDR4000 |
| Manufacturer | Texas Instruments |
| Product Type | Multiplexer |
| Category | Logic |
| Package/Case | 48-ball NFBGA ZBA, 8.00 mm x 3.00 mm body, 0.65 mm pitch |
| Switch Architecture | 12-bit 1:2 or 2:1 high-speed DDR2/DDR3/DDR4 switch/multiplexer; all bits switched simultaneously |
| Supported Signaling Standards | POD_12, SSTL_12, SSTL_15, SSTL_18 |
| Supply Voltage Range | 2.375 to 3.6 V |
| Absolute Maximum VDD | -0.3 to 4.8 V |
| Control Input Voltage Range | -0.3 to 5.5 V for SEL0, SEL1, EN |
| Analog I/O Absolute Voltage Range | -0.3 to 3.6 V for A0-A11, B0-B11, C0-C11 |
| Analog I/O Recommended Voltage Range | 0 to 3.3 V for A0-A11, B0-B11, C0-C11 |
| High-Level Control Input Threshold | 1.4 V to VDD for EN input |
| High-Level Select Input Threshold | 1 V to VDD for SEL0 and SEL1 |
| Low-Level Control Input Threshold | 0 to 0.5 V for EN, SEL0, SEL1 |
| Operating Ambient Temperature | -40 to 85 °C |
| Storage Temperature | -65 to 125 °C |
| HBM ESD Rating | ±3000 V, human body model, JEDEC A114, all pins |
| CDM ESD Rating | ±1000 V, charged device model, JEDEC C101 |
| On-State Resistance A to B | typ 8.3 Ω, max 11.2 Ω at VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| On-State Resistance A to C | typ 8.3 Ω, max 11.2 Ω at VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| On-State Resistance Flatness A to B | typ 0.6 Ω at VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| On-State Resistance Flatness A to C | typ 0.6 Ω at VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| On-State Resistance Channel Match A to B | typ 0.2 Ω, max 1.0 Ω at VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| On-State Resistance Channel Match A to C | typ 0.2 Ω, max 1.0 Ω at VDD=2.375 V, VI/O=1.2 V, II/O=10 mA |
| Control Input High Leakage Current | max ±1 µA for EN/SEL inputs |
| Control Input Low Leakage Current | max ±0.5 µA for EN/SEL inputs, VDD=3.6 V, VIN=0 V |
| Power-Off Leakage Current | max ±5 µA at VDD=0 V, control inputs 0 V or 3.6 V, VI/O=0 to 3.3 V |
| VDD Supply Current, Select Inputs 0 V | typ 28 µA, max 35 µA at VDD=3.6 V, II/O=0 A, EN=0 V |
| VDD Supply Current, Select Inputs 1.8 V | typ 40 µA, max 48 µA at VDD=3.6 V, II/O=0 A, EN=0 V |
| Power-Down Supply Current | typ 2 µA, max 5 µA at VDD=3.6 V, II/O=0 A, EN=1.8 V |
| Switch Turn-On Time EN to B | typ 65 µs, max 140 µs at VDD=2.375 V, RL=50 Ω, VAn=3.3 V |
| Switch Turn-On Time EN to C | typ 65 µs, max 140 µs at VDD=2.375 V, RL=50 Ω, VAn=3.3 V |
| Switching Time Between Channels SEL to B | typ 65 ns at VDD=2.375 V, EN=0 V, RL=50 Ω, VAn=3.3 V |
| Switching Time Between Channels SEL to C | typ 50 ns at VDD=2.375 V, EN=0 V, RL=50 Ω, VAn=3.3 V |
| Propagation Delay A to B | typ 85 ps at VDD=2.375 V |
| Propagation Delay A to C | typ 85 ps at VDD=2.375 V |
| Single-Ended Skew B0 to B11 | typ 3 ps, max 8 ps at VDD=2.375 V, verified by design |
| Single-Ended Skew C0 to C11 | typ 3 ps, max 6 ps at VDD=2.375 V, verified by design |
| Control Input Capacitance | typ 6 pF for EN/SEL inputs, f=1 MHz, VIN=0 V |
| Switch Off Capacitance | typ 0.5 pF for Port A to B or Port A to C, f=1067 MHz, VI/O=0 V |
| Switch On Capacitance | typ 1.0 pF for Port A to B or Port A to C, f=1067 MHz, VI/O=1.2 V |
| Crosstalk Between Channels B0 to B11 | typ -34 dB at f=1067 MHz, select inputs=0 V, RL=50 Ω |
| Crosstalk Between Channels C0 to C11 | typ -31 dB at f=1067 MHz, select inputs=1.8 V, RL=50 Ω |
| Off Isolation | typ -21 dB for Port A to B or Port A to C, f=1067 MHz, RL=50 Ω |
| Insertion Loss | typ -0.75 dB, max -1 dB for Port A to B or Port A to C, f=DC, RL=50 Ω |
| Single-Ended -3 dB Bandwidth | typ 5.6 GHz for Port A to B or Port A to C, RL=50 Ω |
| Differential -3 dB Bandwidth | typ 6 GHz for Port A to B or Port A to C, RL=100 Ω |
| Junction-to-Ambient Thermal Resistance | 92.6 °C/W for 48-ball BGA package |
| Junction-to-Case Top Thermal Resistance | 33.4 °C/W for 48-ball BGA package |
| Junction-to-Board Thermal Resistance | 56.2 °C/W for 48-ball BGA package |
| Datasheet Status | request_only |
Product Overview
The TS3DDR4000 is a Texas Instruments 12-bit DDR2/DDR3/DDR4 switch/multiplexer for Interface applications. Its switch architecture supports 1:2 or 2:1 operation, with all bits switched simultaneously, and it supports POD_12, SSTL_12, SSTL_15, and SSTL_18 signaling standards.
The device operates from a 2.375 to 3.6 V supply and supports analog I/O recommended voltages from 0 to 3.3 V on A0-A11, B0-B11, and C0-C11. Control thresholds are specified separately for EN and SEL inputs, with EN high from 1.4 V to VDD and SEL high from 1 V to VDD.
For high-speed signal paths, the TS3DDR4000 specifies 85 ps typical propagation delay, 3 ps typical single-ended channel skew, 5.6 GHz typical single-ended bandwidth, and 6 GHz typical differential bandwidth. It is packaged in a 48-ball NFBGA ZBA body measuring 8.00 mm x 3.00 mm with 0.65 mm pitch, and is rated for -40 to 85 °C ambient operation.
Key Features
- 12-bit 1:2 or 2:1 DDR switch architecture
- Supports DDR2, DDR3, and DDR4 signal switching
- Compatible with POD_12, SSTL_12, SSTL_15, SSTL_18 standards
- 2.375 to 3.6 V recommended supply range
- 8.3 Ω typical on-state resistance on both paths
- 85 ps typical propagation delay from A to B or C
- 5.6 GHz single-ended and 6 GHz differential bandwidth
- Low 1.0 pF typical switch on capacitance
- -40 to 85 °C ambient operating temperature
- 48-ball NFBGA package with 0.65 mm pitch
Typical Applications
- DDR2 memory signal multiplexing
- DDR3 memory signal switching
- DDR4 interface path selection
- POD_12 signal routing
- SSTL_12 interface switching
- SSTL_15 interface switching
- SSTL_18 interface switching
- High-speed A-to-B or A-to-C routing
Procurement Notes
When requesting a quote for TS3DDR4000, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What type of device is the TS3DDR4000?
The TS3DDR4000 is a Texas Instruments 12-bit 1:2 or 2:1 high-speed DDR2/DDR3/DDR4 switch/multiplexer. Its architecture switches all bits simultaneously for A-to-B or A-to-C signal routing.
What supply voltage range does TS3DDR4000 use?
The recommended VDD operating range is 2.375 to 3.6 V. The datasheet also lists an absolute maximum VDD range of -0.3 to 4.8 V.
Which signaling standards are supported by TS3DDR4000?
The extracted datasheet facts list support for POD_12, SSTL_12, SSTL_15, and SSTL_18 signaling standards, matching its DDR2, DDR3, and DDR4 switch/multiplexer function.
What package is used for the TS3DDR4000?
The TS3DDR4000 is specified in a 48-ball NFBGA ZBA package with an 8.00 mm x 3.00 mm body and 0.65 mm pitch.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.