Specifications
| Type | Description |
|---|---|
| Part Number | ADS1255 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | SSOP-20 |
| Resolution | 24 bit; all specifications at -40°C to +85°C, AVDD=+5V, DVDD=+1.8V, fCLKIN=7.68MHz, PGA=1, VREF=+2.5V unless otherwise noted |
| No Missing Codes | 24 bit; all data rates and PGA settings |
| Noise-Free Resolution | Up to 23 bits; feature description |
| Full-Scale Input Voltage | +/-2VREF/PGA V; AINP - AINN |
| Absolute Analog Input Voltage, Buffer Off | AGND - 0.1 V to AVDD + 0.1 V; AIN0-7, AINCOM to AGND |
| Absolute Analog Input Voltage, Buffer On | AGND to AVDD - 2.0 V; AIN0-7, AINCOM to AGND |
| Programmable Gain Amplifier Range | 1 to 64; binary gain steps |
| Differential Input Impedance, Buffer Off, PGA 1 to 16 | 150/PGA kOhm |
| Differential Input Impedance, Buffer Off, PGA 32 or 64 | 4.7 kOhm |
| Differential Input Impedance, Buffer On | 80 MOhm; fDATA <= 50 Hz |
| Sensor Detect Current Source, SDCS[1:0]=01 | 0.5 uA |
| Sensor Detect Current Source, SDCS[1:0]=10 | 2 uA |
| Sensor Detect Current Source, SDCS[1:0]=11 | 10 uA |
| Data Rate | 2.5 to 30000 SPS; fCLKIN=7.68 MHz |
| Integral Nonlinearity, PGA=1 | typ +/-0.0003 %FSR, max +/-0.0010 %FSR; differential input |
| Integral Nonlinearity, PGA=64 | typ +/-0.0007 %FSR; differential input |
| Offset Error | On the level of the noise; after calibration |
| Offset Drift, PGA=1 | +/-100 nV/°C |
| Offset Drift, PGA=64 | +/-4 nV/°C |
| Gain Error, PGA=1 | +/-0.005 %; after calibration, buffer on |
| Gain Error, PGA=64 | +/-0.03 %; after calibration, buffer on |
| Gain Drift, PGA=1 | +/-0.8 ppm/°C |
| Gain Drift, PGA=64 | +/-0.8 ppm/°C |
| Common-Mode Rejection | min 95 dB, typ 110 dB; fCM=60 Hz, fDATA=30 kSPS |
| AVDD Power-Supply Rejection | min 60 dB, typ 70 dB; +/-5% change in AVDD |
| DVDD Power-Supply Rejection | typ 100 dB; +/-10% change in DVDD |
| Reference Input Voltage | min 0.5 V, typ 2.5 V, max 2.6 V; VREF = VREFP - VREFN |
| Negative Reference Input Range, Buffer Off | AGND - 0.1 V to VREFP - 0.5 V |
| Negative Reference Input Range, Buffer On | AGND to VREFP - 0.5 V; restricted only for self-calibration or gain self-calibration |
| Positive Reference Input Range, Buffer Off | VREFN + 0.5 V to AVDD + 0.1 V |
| Positive Reference Input Range, Buffer On | VREFN + 0.5 V to AVDD - 2.0 V; restricted only for self-calibration or gain self-calibration |
| Voltage Reference Impedance | 18.5 kOhm; fCLKIN=7.68 MHz |
| Digital Input High Voltage, DIN/SCLK/CLKIN/SYNC/CS/RESET | min 0.8 DVDD, max 5.25 V |
| Digital Input High Voltage, D0-D3 | min 0.8 DVDD, max DVDD V |
| Digital Input Low Voltage | DGND to 0.2 DVDD V; digital inputs |
| Digital Output High Voltage | min 0.8 DVDD V; IOH=5 mA |
| Digital Output Low Voltage | max 0.2 DVDD V; IOL=5 mA |
| Input Hysteresis | 0.5 V; digital input/output |
| Input Leakage | +/-10 uA; 0 < VDIGITAL INPUT < DVDD |
| Master Clock Rate, Crystal | min 2 MHz, typ 7.68 MHz, max 10 MHz; external crystal between XTAL1 and XTAL2 |
| Master Clock Rate, External Oscillator | min 0.1 MHz, typ 7.68 MHz, max 10 MHz; external oscillator driving CLKIN |
| Analog Supply Voltage | min 4.75 V, max 5.25 V; AVDD |
| Digital Supply Voltage | min 1.8 V, max 3.6 V; DVDD |
| AVDD Current, Power-Down | 2 uA |
| AVDD Current, Standby | 20 uA |
| AVDD Current, Normal PGA=1 Buffer Off | typ 7 mA, max 10 mA |
| AVDD Current, Normal PGA=64 Buffer Off | typ 16 mA, max 22 mA |
| AVDD Current, Normal PGA=1 Buffer On | typ 13 mA, max 19 mA |
| AVDD Current, Normal PGA=64 Buffer On | typ 36 mA, max 50 mA |
| DVDD Current, Power-Down | 2 uA |
| DVDD Current, Standby | 95 uA; CLKOUT off, DVDD=3.3 V |
| DVDD Current, Normal | typ 0.9 mA, max 2 mA; CLKOUT off, DVDD=3.3 V |
| Power Dissipation, Normal | typ 38 mW, max 57 mW; PGA=1, buffer off, DVDD=3.3 V |
| Power Dissipation, Standby | 0.4 mW; DVDD=3.3 V |
| Specified Temperature Range | -40°C to +85°C; electrical characteristics specified range |
| Operating Temperature Range | -40°C to +105°C; operating free-air temperature range |
| Storage Temperature Range | -60°C to +150°C |
| Analog Supply Absolute Maximum | -0.3 V to +6 V; AVDD to AGND |
| Digital Supply Absolute Maximum | -0.3 V to +3.6 V; DVDD to DGND |
| Ground Differential Absolute Maximum | -0.3 V to +0.3 V; AGND to DGND |
| Input Current Absolute Maximum | 100 mA momentary, 10 mA continuous |
| Analog Input Absolute Maximum | -0.3 V to AVDD + 0.3 V; analog inputs to AGND |
| Digital Input Absolute Maximum | -0.3 V to +6 V; DIN, SCLK, CS, RESET, SYNC/PDWN, XTAL1/CLKIN to DGND |
| Digital I/O Absolute Maximum | -0.3 V to DVDD + 0.3 V; D0/CLKOUT, D1, D2, D3 to DGND |
| Maximum Junction Temperature | +150°C; absolute maximum rating |
| Lead Temperature | +300°C; soldering, 10 s |
| Serial Interface | SPI-compatible, 5 V tolerant; feature description and terminal notes |
| Analog Input Channels | 2 single-ended inputs or 1 differential input with AINCOM; ADS1255 pinout includes AIN0, AIN1, and AINCOM |
| Calibration | Self and system calibration supported for all PGA settings |
| Input Buffer | Chopper-stabilized selectable input buffer |
| PGA Input-Referred Noise | 27 nV; low-noise PGA feature |
| SCLK Period | min 4 tauCLKIN or 10 tauDATA; max 200 ns listed; serial interface timing t1 |
| SCLK High Pulse Width | min 200 ns, max 9 tauDATA; serial interface timing t2H |
| SCLK Low Pulse Width | min 200 ns; serial interface timing t2L |
| CS Setup Time | min 0 ns; CS low to first SCLK, t3; CS can be tied low |
| DIN Setup Time | min 50 ns; valid DIN to SCLK falling edge, t4 |
| DIN Hold Time | min 50 ns; valid DIN to SCLK falling edge, t5 |
| DOUT Propagation Delay | max 50 ns; SCLK rising edge to valid new DOUT; DOUT load=20 pF || 100 kOhm to DGND |
| DOUT Hold Time | min 0 ns; SCLK rising edge to DOUT invalid, t8 |
| RESET/SYNC Pulse Width | min 4 tauCLKIN; RESET, SYNC/PDWN pulse width, t16 |
| DRDY Update Invalid Time | 16 tauCLKIN; conversion data invalid while being updated, t17 |
| Datasheet Status | request_only |
Product Overview
The ADS1255 is a Texas Instruments 24-bit analog-to-digital converter for Signal_Chain designs requiring precision conversion. In the extracted datasheet facts, the device provides 24-bit resolution, no missing codes across all data rates and PGA settings, and noise-free resolution up to 23 bits. Its input range is ±2VREF/PGA, with a programmable gain amplifier from 1 to 64 and selectable input buffering.
The converter supports 2 single-ended inputs or 1 differential input with AINCOM. Buffer-off and buffer-on input limits are specified separately, and differential input impedance depends on PGA and buffer state. The device also includes sensor-detect current source settings of 0.5 µA, 2 µA, and 10 µA.
For system integration, ADS1255 uses an SPI-compatible, 5 V tolerant serial interface. The analog supply range is 4.75 V to 5.25 V, while the digital supply range is 1.8 V to 3.6 V. The SSOP-20 package and -40°C to +105°C operating free-air temperature range support compact precision data-acquisition assemblies.
Key Features
- 24-bit analog-to-digital converter in SSOP-20 package
- No missing codes across data rates and PGA settings
- Noise-free resolution up to 23 bits
- Programmable gain amplifier from 1 to 64
- 2.5 to 30000 SPS data-rate range
- SPI-compatible, 5 V tolerant serial interface
- Selectable chopper-stabilized input buffer
- Self and system calibration for all PGA settings
- Sensor-detect current sources: 0.5, 2, and 10 uA
- Operating free-air temperature range from -40°C to +105°C
Typical Applications
- Precision data acquisition
- Differential signal measurement
- Sensor interface circuits
- Low-frequency high-impedance measurements
- SPI-connected measurement modules
- Calibrated analog front ends
- Wide-gain instrumentation inputs
Procurement Notes
When requesting a quote for ADS1255, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What resolution does the ADS1255 provide?
The ADS1255 provides 24-bit resolution. The extracted datasheet facts also specify no missing codes at all data rates and PGA settings, with noise-free resolution up to 23 bits in the feature description.
What data-rate range is specified for ADS1255?
With fCLKIN at 7.68 MHz, the ADS1255 data-rate range is specified from 2.5 to 30000 SPS. The same facts identify the device as a 24-bit analog-to-digital converter.
What input gain range does the ADS1255 support?
The programmable gain amplifier supports binary gain steps from 1 to 64. Full-scale input voltage is specified as +/-2VREF/PGA for AINP minus AINN.
What supplies are required by the ADS1255?
The analog supply voltage range is 4.75 V to 5.25 V on AVDD. The digital supply voltage range is 1.8 V to 3.6 V on DVDD.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.