Specifications
| Type | Description |
|---|---|
| Part Number | ADS1256 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | SSOP-28 |
| Resolution | 24 bit; all specified conditions: AVDD=5V, DVDD=1.8V, fCLKIN=7.68MHz, PGA=1, VREF=2.5V |
| No Missing Codes | 24 bit; all data rates and PGA settings |
| Noise-Free Resolution | Up to 23 bits; programmable filter optimized for resolution |
| Data Rate | 2.5 to 30000 SPS; fCLKIN=7.68MHz |
| Full-Scale Input Voltage | ±2VREF/PGA V; AINP-AINN |
| Absolute Input Voltage, Buffer Off | AGND - 0.1 to AVDD + 0.1 V; AIN0-7, AINCOM to AGND |
| Absolute Input Voltage, Buffer On | AGND to AVDD - 2.0 V; AIN0-7, AINCOM to AGND |
| Programmable Gain Amplifier | 1 to 64; binary gain steps |
| Differential Input Impedance, Buffer Off, PGA 1-16 | 150/PGA kΩ; PGA=1, 2, 4, 8, 16 |
| Differential Input Impedance, Buffer Off, PGA 32 or 64 | 4.7 kΩ |
| Differential Input Impedance, Buffer On | 80 MΩ; fDATA <= 50Hz |
| Sensor Detect Current Source, SDCS[1:0]=01 | 0.5 µA |
| Sensor Detect Current Source, SDCS[1:0]=10 | 2 µA |
| Sensor Detect Current Source, SDCS[1:0]=11 | 10 µA |
| Integral Nonlinearity, PGA=1 | typ ±0.0003 %FSR, max ±0.0010 %FSR; differential input |
| Integral Nonlinearity, PGA=64 | typ ±0.0007 %FSR; differential input |
| Offset Error | On the level of the noise; after calibration |
| Offset Drift, PGA=1 | ±100 nV/°C |
| Offset Drift, PGA=64 | ±4 nV/°C |
| Gain Error, PGA=1 | ±0.005 %; after calibration, buffer on |
| Gain Error, PGA=64 | ±0.03 %; after calibration, buffer on |
| Gain Drift, PGA=1 | ±0.8 ppm/°C |
| Gain Drift, PGA=64 | ±0.8 ppm/°C |
| Common-Mode Rejection | min 95 dB, typ 110 dB; fCM=60Hz, fDATA=30kSPS |
| AVDD Power-Supply Rejection | min 60 dB, typ 70 dB; ±5% change in AVDD |
| DVDD Power-Supply Rejection | typ 100 dB; ±10% change in DVDD |
| Reference Input Voltage | min 0.5 V, typ 2.5 V, max 2.6 V; VREF = VREFP - VREFN |
| Negative Reference Input Range, Buffer Off | AGND - 0.1 to VREFP - 0.5 V |
| Negative Reference Input Range, Buffer On | AGND to VREFP - 0.5 V |
| Positive Reference Input Range, Buffer Off | VREFN + 0.5 to AVDD + 0.1 V |
| Positive Reference Input Range, Buffer On | VREFN + 0.5 to AVDD - 2.0 V |
| Voltage Reference Impedance | 18.5 kΩ; fCLKIN=7.68MHz |
| Digital Input High Voltage, DIN/SCLK/CLKIN/SYNC/CS/RESET | min 0.8DVDD, max 5.25 V |
| Digital Input High Voltage, D0-D3 | min 0.8DVDD, max DVDD V |
| Digital Input Low Voltage | DGND to 0.2DVDD V; digital inputs |
| Digital Output High Voltage | min 0.8DVDD V; IOH=5mA |
| Digital Output Low Voltage | max 0.2DVDD V; IOL=5mA |
| Digital Input Hysteresis | 0.5 V; digital inputs |
| Digital Input Leakage | ±10 µA; 0 < VDIGITAL INPUT < DVDD |
| Master Clock Rate, Crystal | min 2 MHz, typ 7.68 MHz, max 10 MHz; external crystal between XTAL1 and XTAL2 |
| Master Clock Rate, External Oscillator | min 0.1 MHz, typ 7.68 MHz, max 10 MHz; oscillator driving CLKIN |
| Analog Supply Voltage | 4.75 to 5.25 V; AVDD operating supply |
| Digital Supply Voltage | 1.8 to 3.6 V; DVDD operating supply |
| AVDD Current, Power-Down | 2 µA |
| AVDD Current, Standby | 20 µA |
| AVDD Current, Normal, PGA=1, Buffer Off | typ 7 mA, max 10 mA |
| AVDD Current, Normal, PGA=64, Buffer Off | typ 16 mA, max 22 mA |
| AVDD Current, Normal, PGA=1, Buffer On | typ 13 mA, max 19 mA |
| AVDD Current, Normal, PGA=64, Buffer On | typ 36 mA, max 50 mA |
| DVDD Current, Power-Down | 2 µA |
| DVDD Current, Standby | 95 µA; CLKOUT off, DVDD=3.3V |
| DVDD Current, Normal | typ 0.9 mA, max 2 mA; CLKOUT off, DVDD=3.3V |
| Power Dissipation, Normal | typ 38 mW, max 57 mW; PGA=1, buffer off, DVDD=3.3V |
| Power Dissipation, Standby | 0.4 mW; DVDD=3.3V |
| Specified Temperature Range | -40 to +85 °C; electrical characteristics specified range |
| Operating Temperature Range | -40 to +105 °C; operating free-air temperature range |
| Storage Temperature Range | -60 to +150 °C |
| Analog Input Channels | 8 single-ended or 4 differential inputs; ADS1256 only |
| Serial Interface | SPI-compatible, 5V tolerant |
| Input Buffer | Chopper-stabilized selectable buffer; analog input path |
| PGA Input-Referred Noise | 27 nV; low-noise programmable gain amplifier |
| SCLK Period | min 4τCLKIN or 10τDATA; serial interface timing t1 |
| SCLK High Pulse Width | min 200 ns, max 9τDATA; serial interface timing t2H |
| SCLK Low Pulse Width | min 200 ns; serial interface timing t2L |
| CS Low to First SCLK Setup Time | min 0 ns; serial interface timing t3 |
| DIN Setup Time | min 50 ns; valid DIN to SCLK falling edge, t4 |
| DIN Hold Time | min 50 ns; valid DIN to SCLK falling edge, t5 |
| DOUT Propagation Delay | max 50 ns; SCLK rising edge to valid new DOUT, DOUT load=20pF || 100kΩ to DGND |
| DOUT Hold Time | min 0 ns; SCLK rising edge to DOUT invalid, t8 |
| RESET/SYNC Pulse Width | min 4τCLKIN; RESET, SYNC/PDWN pulse width t16 |
| DRDY Update Invalid Time | 16τCLKIN; conversion data invalid while being updated |
| Maximum Junction Temperature | +150 °C; absolute maximum rating |
| Lead Temperature | +300 °C; soldering, 10 seconds |
| Datasheet Status | request_only |
Product Overview
The ADS1256 is a Texas Instruments 24-bit delta-sigma ADC for Signal_Chain designs requiring multiple precision analog inputs. The device provides 8 single-ended or 4 differential inputs, a selectable chopper-stabilized input buffer, and a programmable gain amplifier with binary gain steps from 1 to 64. Its full-scale differential input range is ±2VREF/PGA, with reference input voltage specified from 0.5 V to 2.6 V and 2.5 V typical.
Conversion performance includes 24-bit resolution, no missing codes to 24 bits across all data rates and PGA settings, and up to 23 bits of noise-free resolution using the programmable filter optimized for resolution. With fCLKIN at 7.68 MHz, the data-rate range is 2.5 to 30000 SPS. Integral nonlinearity is specified at ±0.0003 %FSR typical and ±0.0010 %FSR maximum at PGA=1, and ±0.0007 %FSR typical at PGA=64.
The ADS1256 uses an SSOP-28 package and supports AVDD from 4.75 to 5.25 V with DVDD from 1.8 to 3.6 V. The SPI-compatible serial interface is 5 V tolerant, with specified SCLK, DIN, DOUT, RESET, SYNC, and DRDY timing parameters for digital integration.
Key Features
- 24-bit resolution with no missing codes
- 2.5 to 30000 SPS data-rate range
- Up to 23 bits noise-free resolution
- 8 single-ended or 4 differential inputs
- Programmable gain amplifier from 1 to 64
- Chopper-stabilized selectable analog input buffer
- SPI-compatible serial interface with 5 V tolerance
- 4.75 to 5.25 V analog supply
- 1.8 to 3.6 V digital supply
- SSOP-28 package for board assembly
Typical Applications
- Precision data acquisition systems
- Multichannel sensor measurement
- Differential analog input measurement
- Low-frequency high-resolution conversion
- SPI-connected measurement modules
- Programmable-gain signal measurement
- Sensor detect current applications
Procurement Notes
When requesting a quote for ADS1256, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What resolution does the ADS1256 provide?
The ADS1256 specifies 24-bit resolution under the listed conditions of AVDD=5 V, DVDD=1.8 V, fCLKIN=7.68 MHz, PGA=1, and VREF=2.5 V. It also specifies 24-bit no-missing-codes operation across all data rates and PGA settings.
How many analog inputs are available on the ADS1256?
For the ADS1256, the analog input configuration supports 8 single-ended inputs or 4 differential inputs. The input path also includes a chopper-stabilized selectable buffer and a programmable gain amplifier with binary gain steps from 1 to 64.
What supply voltages does the ADS1256 require?
The analog operating supply, AVDD, is specified from 4.75 to 5.25 V. The digital operating supply, DVDD, is specified from 1.8 to 3.6 V. Normal-mode current depends on PGA setting and whether the input buffer is enabled.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.