Specifications
| Type | Description |
|---|---|
| Part Number | ADS1259 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | PW package, TSSOP-20 |
| Resolution | 24 bits, no missing codes; condition: system performance |
| Output Data Rate | 10 to 14400 SPS; condition: fDATA |
| Full-Scale Input Voltage Range | ±VREF; condition: VIN = AINP - AINN |
| Absolute Analog Input Voltage | AVSS - 0.1 V to AVDD + 0.1 V; condition: AINP, AINN to DGND |
| Differential Input Impedance | 120 kΩ typ; condition: analog inputs |
| Common-Mode Input Impedance | 500 kΩ typ; condition: analog inputs |
| Integral Nonlinearity, ADS1259 | ±0.0003% FSR typ, ±0.001% FSR max; condition: best fit method |
| Integral Nonlinearity, ADS1259B | ±0.00004% FSR typ, ±0.0003% FSR max; condition: best fit method |
| Offset Error | ±40 µV typ, ±250 µV max; condition: system performance |
| Offset Error After Calibration | ±1 µV typ; condition: calibration accuracy at noise level reduced by 16-reading averaging |
| Offset Drift | 0.05 µV/°C typ, 0.25 µV/°C max; condition: TA = -40°C to +105°C |
| Gain Error | ±0.05% typ, ±0.5% max; condition: excludes internal reference error |
| Gain Error After Calibration | ±0.0002% typ; condition: calibration accuracy at noise level reduced by 16-reading averaging |
| Gain Drift | 0.5 ppm/°C typ, 2.5 ppm/°C max; condition: TA = -40°C to +105°C |
| Common-Mode Rejection | 100 dB min, 120 dB typ; condition: 60 Hz AC, fDATA = 14.4 kSPS |
| Input-Referred Noise | 0.7 µV RMS typ; condition: see Table 1; feature text specifies 60 SPS |
| AVDD/AVSS Power-Supply Rejection | 85 dB min, 95 dB typ; condition: 60 Hz AC, fDATA = 14.4 kSPS |
| DVDD Power-Supply Rejection | 85 dB min, 110 dB typ; condition: 60 Hz AC, fDATA = 14.4 kSPS |
| Out-of-Range Detection Threshold Level | ±105% FSR typ; condition: out-of-range detection |
| Out-of-Range Detection Threshold Accuracy | ±0.5% FSR typ; condition: AVSS + 150 mV ≤ AINP or AINN ≤ AVDD - 150 mV |
| Reference Input Range | 0.5 V to 2.5 V min/typ; max AVDD - AVSS + 200 mV; condition: VREF = VREFP - VREFN |
| Negative Reference Absolute Input | AVSS - 100 mV min to VREFP - 0.5 V max; condition: VREFN to DGND |
| Positive Reference Absolute Input | VREFN + 0.5 V min to AVDD + 100 mV max; condition: VREFP to DGND |
| Average Reference Input Current | 200 nA + 60 nA/V typ; condition: AVSS ≤ VREFP or VREFN ≤ AVDD |
| Average Reference Input Current Drift | 0.2 nA/°C typ; condition: internal or external clock |
| Internal Reference Output Voltage | 2.5 V typ; condition: VREFOUT = REFOUT - AVSS |
| Internal Reference Accuracy | ±0.4% typ for ADS1259; ±0.2% typ for ADS1259B; condition: TA = +25°C |
| Internal Reference Temperature Drift, ADS1259 | 10 ppm/°C typ, 40 ppm/°C max; condition: TA = -40°C to +105°C |
| Internal Reference Temperature Drift, ADS1259B | 4 ppm/°C typ, 12 ppm/°C max; condition: TA = -40°C to +105°C |
| Internal Reference Temperature Drift, ADS1259B 0°C to +85°C | 2 ppm/°C typ, 5 ppm/°C max; condition: TA = 0°C to +85°C |
| Reference Output Drive Current | -10 mA to +10 mA; condition: sink and source; limit output current to ±10 mA |
| Reference Load Regulation | 10 µV/mA typ; condition: internal voltage reference |
| Reference Turn-On Settling Time | 1 s typ; condition: ±0.001% settling, CREFOUT = 1 µF, CREFIN = 1 µF |
| Reference Long-Term Stability | 70 ppm/1000 hr typ; condition: 0 to 1000 hours |
| Reference Thermal Hysteresis | 30 ppm typ; condition: see Thermal Hysteresis section |
| Clock Nominal Frequency | 7.3728 MHz typ; condition: clock source fCLK |
| Internal Oscillator Accuracy | ±0.2% typ, ±2% max; condition: internal oscillator |
| Crystal Oscillator Frequency Range | 2 MHz min, 7.3728 MHz typ, 8 MHz max; condition: crystal oscillator |
| Crystal Oscillator Startup Time | 20 ms typ; condition: using 18 pF load capacitors |
| External Clock Frequency Range | 0.1 MHz min, 7.3728 MHz typ, 8 MHz max; condition: external clock |
| External Clock Duty Cycle | 40% min, 60% max; condition: external clock |
| Digital Input High Voltage | 0.8DVDD min to DVDD max; condition: DVDD = 2.7 V to 5.25 V |
| Digital Input Low Voltage | DGND min to 0.2DVDD max; condition: DVDD = 2.7 V to 5.25 V |
| Digital Output High Voltage, IOH = 1 mA | 0.8DVDD min |
| Digital Output High Voltage, IOH = 8 mA | 0.75DVDD min |
| Digital Output Low Voltage | 0.2DVDD max; condition: IOL = 1 mA or 8 mA |
| Digital Input Hysteresis | 0.1 V typ; condition: DVDD = 2.7 V to 5.25 V |
| Digital Input Leakage | ±10 µA max; condition: 0 < VDIGITAL INPUT < DVDD |
| AVSS Supply Voltage | -2.6 V min, 0 V max; condition: power supply |
| AVDD Supply Voltage | AVSS + 4.75 V min to AVSS + 5.25 V max; condition: power supply |
| DVDD Supply Voltage | 2.7 V min to 5.25 V max; condition: power supply |
| AVDD/AVSS Operating Current | 2.3 mA typ, 3.8 mA max; condition: reference enabled |
| AVDD/AVSS Sleep Current, Reference Enabled | 200 µA typ |
| AVDD/AVSS Sleep Current, Reference Disabled | 1 µA typ, 40 µA max |
| AVDD/AVSS Power-Down Current | 1 µA typ, 40 µA max; condition: power-down mode |
| DVDD Operating Current | 500 µA typ, 700 µA max; condition: internal oscillator operating; oscillator current 40 µA typ |
| DVDD Sleep Current | 160 µA typ, 300 µA max; condition: sleep mode |
| DVDD Power-Down Current | 1 µA typ, 10 µA max; condition: external CLKIN and SCLK stopped; digital inputs at VIH or VIL |
| Operating Power Dissipation | 13 mW typ, 22 mW max; condition: operating mode |
| Sleep Power Dissipation, Reference Enabled | 1.5 mW typ |
| Sleep Power Dissipation, Reference Disabled | 0.5 mW typ, 1.2 mW max |
| Power-Down Dissipation | 10 µW typ, 240 µW max; condition: power-down mode |
| Specified Temperature Range | -40°C to +105°C; condition: electrical characteristics |
| Operating Temperature Range | -40°C to +125°C; condition: electrical characteristics and absolute maximum ratings |
| Storage Temperature Range | -60°C to +150°C; condition: electrical characteristics and absolute maximum ratings |
| Maximum Junction Temperature | +150°C max; condition: absolute maximum ratings |
| Analog Supply Absolute Maximum | -0.3 V to +5.5 V; condition: AVDD to AVSS |
| AVSS to DGND Absolute Maximum | -2.8 V to +0.3 V; condition: absolute maximum ratings |
| Digital Supply Absolute Maximum | -0.3 V to +5.5 V; condition: DVDD to DGND |
| Momentary Input Current Absolute Maximum | -100 mA to +100 mA; condition: absolute maximum ratings |
| Continuous Input Current Absolute Maximum | -10 mA to +10 mA; condition: absolute maximum ratings |
| Analog Input Voltage Absolute Maximum | AVSS - 0.3 V to AVDD + 0.3 V; condition: analog input voltage to DGND |
| Digital Input Voltage Absolute Maximum | -0.3 V to DVDD + 0.3 V; condition: digital input voltage to DGND |
| Serial Interface Maximum Clock Rate | 4 MHz; condition: SPI-compatible interface described in product description |
| SPI CS Low to First SCLK Setup Time | 50 ns min; condition: tCSSC; CS can be tied low |
| SPI SCLK Period | 1.8 × tCLK min; condition: tSCLK, tCLK = 1/fCLK |
| SPI SCLK High Pulse Width | 90 ns min; condition: tSPWH |
| SPI SCLK Low Pulse Width | 90 ns min or 216 × tCLK max condition noted for reset; condition: tSPWL |
| SPI DIN Setup Time | 35 ns min; condition: valid DIN to SCLK falling edge, tDIST |
| SPI DIN Hold Time | 20 ns min; condition: valid DIN to SCLK falling edge, tDIHD |
| SPI DOUT Propagation Delay | 60 ns max; condition: SCLK rising edge to valid new DOUT, DOUT load = 20 pF || 100 kΩ to DGND |
| SPI DOUT Hold Time | 0 ns min; condition: SCLK rising edge to DOUT invalid, tDOHD |
| SPI CS Low to DOUT Driven Delay | 0 ns min, 40 ns max; condition: tCSDOD; DOUT load = 20 pF || 100 kΩ to DGND |
| SPI CS High to DOUT Hi-Z Delay | 20 ns max; condition: tCSDOZ |
| SPI CS High Pulse Width | 20 × tCLK min; condition: tCSH |
| Pin Count | 20 pins; condition: PW package TSSOP-20 pin configuration |
| Interface | SPI-compatible; condition: CS, SCLK, DIN, DOUT pins; serial interface |
| Conversion Synchronization | Command or pin synchronized; condition: product description |
| Digital Filter Settling | Single-cycle settling available; condition: fast settling mode |
| Line Rejection | Simultaneous 50/60 Hz rejection at 10 SPS; condition: feature list |
| Datasheet Status | request_only |
Product Overview
The ADS1259 is a Texas Instruments 24-bit delta-sigma ADC for Signal_Chain designs that require differential conversion with no missing codes. Its analog input span is defined as VIN = AINP - AINN with a full-scale range of ±VREF, and the output data rate is programmable from 10 to 14400 SPS. The analog inputs specify 120 kΩ typical differential input impedance and 500 kΩ typical common-mode input impedance.
Accuracy-related specifications include ±40 µV typical offset error, ±1 µV typical offset error after calibration with 16-reading averaging, and 0.05 µV/°C typical offset drift over -40°C to +105°C. Gain error is ±0.05% typical before calibration and ±0.0002% typical after calibration. The ADS1259B variant has tighter INL and reference-drift entries in the extracted datasheet data.
The device uses a SPI-compatible interface with CS, SCLK, DIN, and DOUT pins and supports a 4 MHz maximum serial clock rate. It is offered in a 20-pin PW TSSOP-20 package. Supply operation includes AVDD from AVSS + 4.75 V to AVSS + 5.25 V, DVDD from 2.7 V to 5.25 V, and specified electrical characteristics from -40°C to +105°C.
Key Features
- 24-bit delta-sigma conversion with no missing codes
- Output data rate range from 10 to 14400 SPS
- ±VREF full-scale differential analog input range
- 0.7 µV RMS typical input-referred noise at 60 SPS
- 100 dB minimum common-mode rejection at 60 Hz
- SPI-compatible interface with 4 MHz maximum clock rate
- Command or pin synchronized conversion control
- Single-cycle settling available in fast settling mode
- Integrated 2.5 V typical reference output
- Simultaneous 50/60 Hz rejection at 10 SPS
- 13 mW typical operating power dissipation
- PW package, TSSOP-20 with 20 pins
Typical Applications
- Precision differential data acquisition
- Reference-based measurement channels
- SPI-connected converter modules
- Synchronized conversion systems
- Low-noise sensor signal conversion
- 50/60 Hz rejected measurements
- Temperature-rated industrial signal chains
Procurement Notes
When requesting a quote for ADS1259, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What resolution does the ADS1259 provide?
The ADS1259 provides 24-bit delta-sigma conversion with no missing codes. The extracted datasheet facts list this resolution under system performance, with an output data rate range from 10 to 14400 SPS.
What interface is used by the ADS1259?
The ADS1259 uses a SPI-compatible serial interface with CS, SCLK, DIN, and DOUT pins. The extracted data lists a 4 MHz maximum serial interface clock rate and timing parameters for chip select, SCLK, DIN, and DOUT.
What package is specified for the ADS1259?
The extracted datasheet facts specify the PW package, TSSOP-20. The pin configuration fact lists 20 pins for this package, matching the package_case field used for CMS content.
What reference options are described for the ADS1259?
The ADS1259 facts include a 2.5 V typical internal reference output, a 0.5 V to 2.5 V reference input range, ±10 mA reference output drive current, and reference settling, stability, load regulation, and drift specifications.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.