Specifications
| Type | Description |
|---|---|
| Part Number | AT24C08N |
| Manufacturer | ATMEL |
| Product Type | EEPROM |
| Category | Memory & Storage |
| Package/Case | 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP MLP 2x3, 5-lead SOT23, 8-lead TSSOP, 8-ball dBGA2 |
| Memory Density | 8192 bits; condition: AT24C08A family member |
| Memory Organization | 1024 x 8; condition: 8K serial EEPROM |
| Internal Page Organization | 64 pages of 16 bytes each; condition: AT24C08A |
| Random Address Width | 10-bit data word address; condition: AT24C08A |
| Serial Interface | Two-wire serial interface; condition: SCL and SDA pins |
| SDA Pin Type | Bidirectional open-drain; condition: may be wire-ORed with other open-drain/open-collector devices |
| Clock Frequency | 100 kHz max; condition: VCC = 1.8 V to 5.5 V |
| Clock Frequency | 400 kHz max; condition: VCC = 2.7 V to 5.5 V or 5.0 V operation |
| Supply Voltage | 1.8 V min, 5.5 V max; condition: VCC1 recommended operating range |
| Supply Voltage | 2.7 V min, 5.5 V max; condition: VCC2 recommended operating range |
| Supply Voltage | 4.5 V min, 5.5 V max; condition: VCC3 recommended operating range |
| Read Supply Current | 0.4 mA typ, 1.0 mA max; condition: VCC = 5.0 V, read at 100 kHz |
| Write Supply Current | 2.0 mA typ, 3.0 mA max; condition: VCC = 5.0 V, write at 100 kHz |
| Standby Current | 0.6 µA typ, 3.0 µA max; condition: VCC = 1.8 V, VIN = VCC or VSS |
| Standby Current | 1.4 µA typ, 4.0 µA max; condition: VCC = 2.5 V, VIN = VCC or VSS |
| Standby Current | 1.6 µA typ, 4.0 µA max; condition: VCC = 2.7 V, VIN = VCC or VSS |
| Standby Current | 8.0 µA typ, 18.0 µA max; condition: VCC = 5.0 V, VIN = VCC or VSS |
| Input Leakage Current | 0.10 µA typ, 3.0 µA max; condition: VIN = VCC or VSS |
| Output Leakage Current | 0.05 µA typ, 3.0 µA max; condition: VOUT = VCC or VSS |
| Input Low Voltage | -0.6 V min, 0.3 x VCC max; condition: reference only, not tested |
| Input High Voltage | 0.7 x VCC min, VCC + 0.5 V max; condition: reference only, not tested |
| Output Low Voltage | 0.4 V max; condition: VCC = 3.0 V, IOL = 2.1 mA |
| Output Low Voltage | 0.2 V max; condition: VCC = 1.8 V, IOL = 0.15 mA |
| Input/Output Capacitance | 8 pF max; condition: SDA, TA = 25°C, f = 1.0 MHz, VCC = 1.8 V, VI/O = 0 V; characterized, not 100% tested |
| Input Capacitance | 6 pF max; condition: A0, A1, A2, SCL; TA = 25°C, f = 1.0 MHz, VCC = 1.8 V, VIN = 0 V; characterized, not 100% tested |
| Clock Pulse Width Low | 4.7 µs min; condition: 1.8 V operation |
| Clock Pulse Width Low | 1.2 µs min; condition: 2.7 V or 5.0 V operation |
| Clock Pulse Width High | 4.0 µs min; condition: 1.8 V operation |
| Clock Pulse Width High | 0.6 µs min; condition: 2.7 V or 5.0 V operation |
| Noise Suppression Time | 100 ns max; condition: 1.8 V operation; characterized |
| Noise Suppression Time | 50 ns max; condition: 2.7 V or 5.0 V operation; characterized |
| Clock Low to Data Out Valid | 0.1 µs min, 4.5 µs max; condition: 1.8 V operation |
| Clock Low to Data Out Valid | 0.1 µs min, 0.9 µs max; condition: 2.7 V or 5.0 V operation |
| Bus Free Time Before New Transmission | 4.7 µs min; condition: 1.8 V operation; characterized |
| Bus Free Time Before New Transmission | 1.2 µs min; condition: 2.7 V or 5.0 V operation; characterized |
| Start Hold Time | 4.0 µs min; condition: 1.8 V operation |
| Start Hold Time | 0.6 µs min; condition: 2.7 V or 5.0 V operation |
| Start Setup Time | 4.7 µs min; condition: 1.8 V operation |
| Start Setup Time | 0.6 µs min; condition: 2.7 V or 5.0 V operation |
| Data In Hold Time | 0 µs min; condition: 1.8 V and 2.7 V/5.0 V operation |
| Data In Setup Time | 200 ns min; condition: 1.8 V operation |
| Data In Setup Time | 100 ns min; condition: 2.7 V or 5.0 V operation |
| Input Rise Time | 1.0 µs max; condition: 1.8 V operation; characterized |
| Input Rise Time | 0.3 µs max; condition: 2.7 V or 5.0 V operation; characterized |
| Input Fall Time | 300 ns max; condition: 1.8 V and 2.7 V/5.0 V operation; characterized |
| Stop Setup Time | 4.7 µs min; condition: 1.8 V operation |
| Stop Setup Time | 0.6 µs min; condition: 2.7 V or 5.0 V operation |
| Data Out Hold Time | 100 ns min; condition: 1.8 V operation |
| Data Out Hold Time | 50 ns min; condition: 2.7 V or 5.0 V operation |
| Write Cycle Time | 5 ms max; condition: 1.8 V and 2.7 V/5.0 V operation |
| Write Endurance | 1,000,000 cycles; condition: 5.0 V, 25°C, byte mode; characterized |
| Data Retention | 100 years; condition: high-reliability feature |
| Page Write Size | 16 bytes; condition: AT24C08A page write |
| Partial Page Writes | Allowed; condition: serial EEPROM write mode |
| Write Protect Function | Full 8K array protected when WP = VCC; normal read/write when WP = GND; condition: AT24C08A |
| Device Address Inputs | A2 used; A1 and A0 are no connect; condition: AT24C08A hardwire addressing |
| Maximum Devices Per Bus | 2 devices; condition: AT24C08A uses only A2 hardwire address input |
| Operating Temperature Range | -40°C to +85°C; condition: recommended operating range for DC and AC characteristics |
| Absolute Maximum Operating Temperature | -55°C to +125°C; condition: absolute maximum ratings |
| Storage Temperature Range | -65°C to +150°C; condition: absolute maximum ratings |
| Voltage on Any Pin | -1.0 V to +7.0 V; condition: with respect to ground; absolute maximum rating |
| Maximum Operating Voltage | 6.25 V; condition: absolute maximum rating |
| DC Output Current | 5.0 mA; condition: absolute maximum rating |
| Datasheet Status | request_only |
Product Overview
AT24C08N is a ATMEL two-wire serial EEPROM in the Memory category. The device provides 8192 bits of nonvolatile storage organized as 1024 x 8, with 64 pages of 16 bytes each. Random addressing uses a 10-bit data word address, and page write operation supports 16-byte page writes with partial page writes allowed.
The serial interface uses SCL and SDA pins. SDA is a bidirectional open-drain pin that may be wire-ORed with other open-drain or open-collector devices. Clock frequency is specified to 100 kHz maximum across the 1.8 V to 5.5 V range and 400 kHz maximum for 2.7 V to 5.5 V or 5.0 V operation.
Package options include 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP MLP 2x3, 5-lead SOT23, 8-lead TSSOP, and 8-ball dBGA2. The device is suited to compact serial memory designs requiring low standby current, write protection, page write capability, and operation from -40°C to +85°C.
Key Features
- 8192-bit serial EEPROM organized as 1024 x 8
- 64 internal pages with 16 bytes per page
- Two-wire serial interface using SCL and SDA pins
- Bidirectional open-drain SDA supports wired bus connection
- 100 kHz operation across 1.8 V to 5.5 V
- 400 kHz operation at 2.7 V to 5.5 V
- Write cycle time specified to 5 ms maximum
- Write endurance characterized to 1,000,000 cycles
- Data retention specified as 100 years
- Write protect covers full 8K array when WP equals VCC
Typical Applications
- Board configuration storage
- Serial parameter memory
- Device identification storage
- Calibration data storage
- Low-current embedded memory
- Two-wire bus memory expansion
- Protected EEPROM data storage
Procurement Notes
When requesting a quote for AT24C08N, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For memory and storage sourcing, density, organization, speed grade, voltage, package, temperature grade, date code, lifecycle status and original packing condition should be verified before approval.
FAQ
What memory density does AT24C08N provide?
AT24C08N provides 8192 bits of EEPROM memory. The extracted organization is 1024 x 8, with 64 internal pages of 16 bytes each for the AT24C08A family member.
What serial interface does AT24C08N use?
AT24C08N uses a two-wire serial interface with SCL and SDA pins. The SDA pin is bidirectional open-drain and may be wire-ORed with other open-drain or open-collector devices.
What clock rates are specified for AT24C08N?
The clock frequency is 100 kHz maximum when VCC is 1.8 V to 5.5 V. For VCC from 2.7 V to 5.5 V or 5.0 V operation, the maximum clock frequency is 400 kHz.
How does write protection work on AT24C08N?
For the AT24C08A configuration, the full 8K array is protected when WP is connected to VCC. Normal read and write operation is available when WP is connected to GND.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.