AT24C256_AT24C512 Two-Wire Serial EEPROM

ATMEL Memory — specifications, applications, sourcing support and RFQ.

AT24C256_AT24C512 Two-Wire Serial EEPROM

RFQ Available Sourcing Support Alternative Matching RoHS
Part Number
AT24C256_AT24C512
Manufacturer
ATMEL
Package
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, 8-lead SAP, 8-ball dBGA2; dimensions not provided in supplied text
Category
Memory & Storage
Product Type
NOR Flash

Quick Sourcing Note

AT24C256_AT24C512 is listed as a ATMEL Memory product and described by the supplied facts as a two-wire serial EEPROM family. The datasheet text specifically covers AT24C128/AT24C256 with 131,072/262,144-bit density and 16,384 x 8 / 32,768 x 8 organization. Package options include 8-lead JEDEC PDIP, JEDEC SOIC, EIAJ SOIC, MAP, TSSOP, SAP, and 8-ball dBGA2. Key parameters include 64-byte page writes, up to four devices per bus using A1/A0, 1.8 V to 3.6 V and 2.7 V to 5.5 V supply options, 100 kHz to 1000 kHz clock operation, write protection, and industrial or extended temperature ranges.

Specifications

TypeDescription
Part NumberAT24C256_AT24C512
ManufacturerATMEL
Product TypeNOR Flash
CategoryMemory & Storage
Package/Case8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, 8-lead SAP, 8-ball dBGA2; dimensions not provided in supplied text
Inferred CategoryMemory
Component TypeMemory
Part Number Source NoteProvided product information; supplied datasheet text specifically describes AT24C128/AT24C256
Manufacturer Source NoteProvided product information; supplied datasheet text references Atmel
Memory Density131,072/262,144 bits; AT24C128/AT24C256
Memory Organization16,384 x 8 / 32,768 x 8; AT24C128/AT24C256 respectively
InterfaceTwo-wire serial interface; serial EEPROM bus interface
Maximum Devices per BusUp to 4 devices using A1 and A0 device address inputs
Page Write Size64 bytes; partial page writes allowed
Internal Page Organization256/512 pages of 64 bytes each; AT24C128/AT24C256 respectively
Random Word Address Width14/15-bit data word address; AT24C128/AT24C256 respectively
Supply Voltage Option1.8 V to 3.6 V; 1.8 V version
Supply Voltage Option2.7 V to 5.5 V; 2.7 V version
Supply Voltage VCC1Min 1.8 V, Max 3.6 V; recommended operating range
Supply Voltage VCC2Min 2.5 V, Max 5.5 V; recommended operating range
Supply Voltage VCC3Min 4.5 V, Max 5.5 V; recommended operating range
Clock Frequency100 kHz; 1.8 V industrial operation
Clock Frequency400 kHz; 2.5 V industrial operation or 2.7 V extended operation
Clock Frequency1000 kHz; 5.0 V industrial or extended operation
Supply Current ICC1Typ 1.0 mA, Max 2.0 mA; VCC=5.0 V, READ at 400 kHz
Supply Current ICC2Typ 2.0 mA, Max 3.0 mA; VCC=5.0 V, WRITE at 400 kHz
Standby Current ISB1Typ 0.2 uA, Max 2.0 uA; 1.8 V option, VCC=1.8 V to 3.6 V, VIN=VCC or VSS
Standby Current ISB2Typ 0.5 uA, Max 6.0 uA; 2.5 V option, VCC=2.5 V to 5.5 V, VIN=VCC or VSS
Standby Current ISB3Max 6.0 uA; 5.0 V option, VCC=4.5 V to 5.5 V, VIN=VCC or VSS
Input Leakage Current ILITyp 0.10 uA, Max 3.0 uA; VIN=VCC or VSS
Output Leakage Current ILOTyp 0.05 uA, Max 3.0 uA; VOUT=VCC or VSS
Input Low Voltage VILMin -0.6 V, Max VCC x 0.3 V; reference only, not tested
Input High Voltage VIHMin VCC x 0.7 V, Max VCC + 0.5 V; reference only, not tested
Output Low Voltage VOL2Max 0.4 V; VCC=3.0 V, IOL=2.1 mA
Output Low Voltage VOL1Max 0.2 V; VCC=1.8 V, IOL=0.15 mA
SDA CapacitanceMax 8 pF; VI/O=0 V, TA=25 C, f=1.0 MHz, VCC=1.8 V; characterized, not 100% tested
Input CapacitanceMax 6 pF; A0, A1, SCL; VIN=0 V, TA=25 C, f=1.0 MHz, VCC=1.8 V; characterized, not 100% tested
Industrial Operating Temperature-40 C to +85 C; TAI, VCC=1.8 V to 5.5 V
Extended Operating Temperature-40 C to +125 C; TAE, VCC=2.7 V to 5.5 V; process letter B devices
Absolute Operating Temperature-55 C to +125 C; absolute maximum rating
Storage Temperature-65 C to +150 C; absolute maximum rating
Voltage on Any Pin-1.0 V to +7.0 V with respect to ground; absolute maximum rating
Maximum Operating Voltage6.25 V; absolute maximum rating
DC Output Current5.0 mA; absolute maximum rating
Write Cycle TimeMax 5 ms; self-timed write cycle; process letter B devices
Write Cycle Time tWR20 or 5 ms; 1.8 V industrial operation; 5 ms applies to process letter B devices
Write Cycle Time tWR10 or 5 ms; 2.5 V/5.0 V industrial or 2.7 V/5.0 V extended operation; 5 ms applies to process letter B devices
Write Endurance100k or 1,000,000 cycles; 25 C, page mode; 1,000,000 cycles guaranteed for process letter B devices at 1.8 V to 3.6 V
Data Retention40 years; high reliability feature
SCL Low Pulse Width tLOWMin 4.7 us / 1.3 us / 0.4 us; industrial 1.8 V / 2.5 V / 5.0 V operation
SCL High Pulse Width tHIGHMin 4.0 us / 0.6 us / 0.4 us; industrial 1.8 V / 2.5 V / 5.0 V operation
Clock Low to Data Out Valid tAA0.1-4.5 us / 0.05-0.9 us / 0.05-0.55 us; industrial 1.8 V / 2.5 V / 5.0 V operation
Bus Free Time tBUFMin 4.7 us / 1.3 us / 0.5 us; industrial 1.8 V / 2.5 V / 5.0 V operation
Start Hold Time tHD.STAMin 4.0 us / 0.6 us / 0.25 us; industrial 1.8 V / 2.5 V / 5.0 V operation
Start Setup Time tSU.STAMin 4.7 us / 0.6 us / 0.25 us; industrial 1.8 V / 2.5 V / 5.0 V operation
Data Input Hold Time tHD.DATMin 0 us; industrial 1.8 V / 2.5 V / 5.0 V operation
Data Input Setup Time tSU.DATMin 200 ns / 100 ns / 100 ns; industrial 1.8 V / 2.5 V / 5.0 V operation
Input Rise Time tRMax 1.0 us / 0.3 us / 0.3 us; industrial 1.8 V / 2.5 V / 5.0 V operation; characterized, not 100% tested
Input Fall Time tFMax 300 ns / 300 ns / 100 ns; industrial 1.8 V / 2.5 V / 5.0 V operation; characterized, not 100% tested
Stop Setup Time tSU.STOMin 4.7 us / 0.6 us / 0.25 us; industrial 1.8 V / 2.5 V / 5.0 V operation
Data Out Hold Time tDHMin 100 ns / 50 ns / 50 ns; industrial 1.8 V / 2.5 V / 5.0 V operation
Extended SCL Low Pulse Width tLOWMin 1.3 us / 0.4 us; extended 2.7 V / 5.0 V operation
Extended SCL High Pulse Width tHIGHMin 0.6 us / 0.4 us; extended 2.7 V / 5.0 V operation
Extended Clock Low to Data Out Valid tAA0.05-0.9 us / 0.05-0.55 us; extended 2.7 V / 5.0 V operation
Extended Bus Free Time tBUFMin 1.3 us / 0.5 us; extended 2.7 V / 5.0 V operation
Extended Data Input Setup Time tSU.DATMin 100 ns; extended 2.7 V / 5.0 V operation
Extended Data Out Hold Time tDHMin 50 ns; extended 2.7 V / 5.0 V operation
Write Protect FunctionWP high inhibits all memory write operations; WP to GND allows normal writes; hardware data protection for whole memory
SDA Output TypeOpen-drain bidirectional serial data; may be wire-ORed with other open-drain or open-collector devices
Device Address Word8-bit address word with fixed leading one-zero sequence and A1/A0 address bits; read/write operation selected by eighth bit
Package AvailabilityLead-free/halogen-free devices available
Design Status NoteAT24C256 not recommended for new design; refer to AT24C256B datasheet
Datasheet Statusrequest_only

Product Overview

AT24C256_AT24C512 is categorized as a Memory component and product type two-wire serial EEPROM. The extracted datasheet facts specifically describe AT24C128/AT24C256 behavior, including 131,072/262,144-bit memory density and 16,384 x 8 / 32,768 x 8 organization. The devices use a two-wire serial interface and support up to four devices on the same bus through A1 and A0 device address inputs.

The memory array is organized as 256/512 pages of 64 bytes each, with partial page writes allowed. Random word addressing uses 14/15-bit data word addresses for AT24C128/AT24C256 respectively. Write operation details include a self-timed write cycle with a 5 ms maximum for process letter B devices, while endurance is specified as 100k or 1,000,000 cycles depending on condition.

Package availability spans 8-lead JEDEC PDIP, JEDEC SOIC, EIAJ SOIC, MAP, TSSOP, SAP, and 8-ball dBGA2. Electrical coverage includes supply ranges from 1.8 V to 5.5 V across listed options, standby current down to 0.2 uA typical for the 1.8 V option, open-drain bidirectional SDA, and hardware write protection using WP. The datasheet also notes AT24C256 is not recommended for new design and refers designers to AT24C256B.

Key Features

  • Two-wire serial EEPROM memory interface
  • 131,072/262,144-bit density options
  • 16,384 x 8 / 32,768 x 8 organization
  • 64-byte page write operation
  • Partial page writes are allowed
  • Up to four devices per bus
  • Open-drain bidirectional SDA output
  • Hardware write protection through WP pin
  • 1.8 V to 5.5 V operating ranges
  • Industrial and extended temperature operation
  • 40-year data retention specification
  • Lead-free/halogen-free devices available

Typical Applications

  • Two-wire EEPROM memory storage
  • Addressed serial memory buses
  • Multi-device EEPROM bus designs
  • Hardware write-protected memory
  • Industrial temperature memory systems
  • Extended temperature memory systems
  • 64-byte page write storage
  • Open-drain serial data buses

Procurement Notes

When requesting a quote for AT24C256_AT24C512, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.

If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.

For memory and storage sourcing, density, organization, speed grade, voltage, package, temperature grade, date code, lifecycle status and original packing condition should be verified before approval.

FAQ

What memory type is AT24C256_AT24C512?

AT24C256_AT24C512 is listed as a Memory component and described by the extracted facts as a two-wire serial EEPROM. The supplied datasheet text specifically describes AT24C128/AT24C256 behavior.

What package options are listed for this EEPROM?

The listed package options are 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, 8-lead SAP, and 8-ball dBGA2. Dimensions were not provided in the supplied text.

How many devices can share the serial bus?

The extracted facts specify up to four devices on the bus when using the A1 and A0 device address inputs. The device address word uses fixed leading bits plus A1/A0 address bits.

What does the WP pin do?

The write protect input provides hardware data protection for the whole memory. When WP is high, all memory write operations are inhibited; connecting WP to GND allows normal write operations.

Is AT24C256 recommended for new designs?

The datasheet note states that AT24C256 is not recommended for new design and directs designers to the AT24C256B datasheet. This note applies to the supplied datasheet facts.

Technical Review & Sourcing Note

Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.

This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.

Request Quote Request Datasheet