Specifications
| Type | Description |
|---|---|
| Part Number | AT24C256 |
| Manufacturer | Atmel |
| Product Type | DRAM |
| Category | Memory & Storage |
| Package / Case | 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead SAP, 8-ball dBGA2 |
| Memory Density | 262,144 bits; AT24C256 |
| Memory Organization | 32,768 x 8; AT24C256 |
| Page Organization | 512 pages of 64 bytes each; AT24C256 |
| Page Write Size | 64 bytes; partial page writes allowed |
| Random Word Address Width | 15-bit data word address; AT24C256 |
| Serial Interface | Two-wire serial interface; SCL and SDA pins |
| Maximum Devices on Bus | 4 devices; using A1 and A0 device address inputs |
| Device Address Pins | A1, A0; hardwired or left not connected; internally biased low if floating and capacitive coupling to VCC plane is <3 pF |
| Write Protect Function | Whole memory write protected when WP is high to VCC; WP connected to VCC |
| Normal Write Enable | Normal write operations allowed; WP connected to GND |
| Supply Voltage | 1.8-3.6 V; VCC1 recommended operating range |
| Supply Voltage | 2.5-5.5 V; VCC2 recommended operating range |
| Supply Voltage | 4.5-5.5 V; VCC3 recommended operating range |
| Operating Temperature | -40°C to +85°C; industrial temperature range, TAI |
| Operating Temperature | -40°C to +125°C; extended temperature range, TAE, VCC=2.7V to 5.5V; process letter B devices |
| Absolute Maximum Operating Temperature | -55°C to +125°C; absolute maximum rating |
| Storage Temperature | -65°C to +150°C; absolute maximum rating |
| Voltage on Any Pin | -1.0 V to +7.0 V; with respect to ground, absolute maximum rating |
| Maximum Operating Voltage | 6.25 V; absolute maximum rating |
| DC Output Current | 5.0 mA; absolute maximum rating |
| Input/Output Capacitance | Max 8 pF; SDA, TA=25°C, f=1.0 MHz, VCC=+1.8V, VI/O=0V |
| Input Capacitance | Max 6 pF; A0, A1, SCL; TA=25°C, f=1.0 MHz, VCC=+1.8V, VIN=0V |
| Read Supply Current | Typ 1.0 mA, Max 2.0 mA; VCC=5.0V, read at 400 kHz |
| Write Supply Current | Typ 2.0 mA, Max 3.0 mA; VCC=5.0V, write at 400 kHz |
| Standby Current | Typ 0.2 µA, Max 2.0 µA; 1.8V option, VCC=1.8V to 3.6V, VIN=VCC or VSS |
| Standby Current | Typ 0.5 µA, Max 6.0 µA; 2.5V option, VCC=2.5V to 5.5V, VIN=VCC or VSS |
| Standby Current | Max 6.0 µA; 5.0V option, VCC=4.5V to 5.5V, VIN=VCC or VSS |
| Input Leakage Current | Typ 0.10 µA, Max 3.0 µA; VIN=VCC or VSS |
| Output Leakage Current | Typ 0.05 µA, Max 3.0 µA; VOUT=VCC or VSS |
| Input Low Voltage | Min -0.6 V, Max VCC x 0.3 V; VIL reference only, not tested |
| Input High Voltage | Min VCC x 0.7 V, Max VCC + 0.5 V; VIH reference only, not tested |
| Output Low Voltage | Max 0.4 V; VCC=3.0V, IOL=2.1 mA |
| Output Low Voltage | Max 0.2 V; VCC=1.8V, IOL=0.15 mA |
| Clock Frequency | Max 100 kHz; 1.8V industrial operation |
| Clock Frequency | Max 400 kHz; 2.5V industrial operation or 2.7V extended operation |
| Clock Frequency | Max 1000 kHz; 5.0V industrial or extended operation |
| Write Cycle Time | Max 5 ms; self-timed write cycle; applies to process letter B devices |
| Write Cycle Time | Max 10 ms or 5 ms; 2.5V and 5.0V industrial operation; 5 ms for process letter B devices |
| Write Cycle Time | Max 20 ms or 5 ms; 1.8V industrial operation; 5 ms for process letter B devices |
| Write Endurance | 100,000 or 1,000,000 cycles; 25°C, page mode; 1,000,000 cycles for process letter B devices at 1.8V to 3.6V |
| Data Retention | 40 years; high reliability feature |
| Datasheet Status | request_only |
Product Overview
The AT24C256 is an Atmel two-wire serial EEPROM in the Memory & Storage category. It provides 262,144 bits of nonvolatile memory arranged as 32,768 x 8, with a 15-bit data word address. The array is organized as 512 pages of 64 bytes each, and page write operations support 64 bytes with partial page writes allowed.
The serial interface uses SCL and SDA pins. A1 and A0 are device address inputs, allowing up to four devices on the same bus. These address pins may be hardwired or left not connected when their floating condition remains internally biased low under the stated capacitive coupling condition.
Supported package cases include 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead SAP, and 8-ball dBGA2. Supply options span 1.8-3.6 V, 2.5-5.5 V, and 4.5-5.5 V recommended operating ranges. Clock frequency depends on operating condition, from 100 kHz at 1.8 V industrial operation to 1000 kHz at 5.0 V industrial or extended operation.
Key Features
- 262,144-bit EEPROM organized as 32,768 x 8
- 512 pages with 64 bytes per page
- Two-wire serial interface using SCL and SDA
- 15-bit data word address for random access
- Up to four devices using A1 and A0
- Whole memory write protection through WP high
- Normal write operations with WP connected to GND
- Recommended supply ranges from 1.8 V to 5.5 V
- Clock operation up to 1000 kHz at 5.0 V
- Data retention specified for 40 years
Typical Applications
- Two-wire EEPROM storage
- Nonvolatile parameter storage
- Serial memory expansion
- Board configuration memory
- Calibration data storage
- Industrial temperature memory designs
- Multi-device serial memory buses
Procurement Notes
When requesting a quote for AT24C256, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For memory and storage sourcing, density, organization, speed grade, voltage, package, temperature grade, date code, lifecycle status and original packing condition should be verified before approval.
FAQ
What memory density does the AT24C256 provide?
The AT24C256 provides 262,144 bits of EEPROM memory. The datasheet organization is 32,768 x 8, with the memory arranged as 512 pages of 64 bytes each.
Which interface pins are used by the AT24C256?
The AT24C256 uses a two-wire serial interface through SCL and SDA pins. Device addressing is handled with A1 and A0 inputs, which support up to four devices on the same bus.
How does write protection work on the AT24C256?
When WP is connected high to VCC, the whole memory is write protected. Normal write operations are allowed when WP is connected to GND, according to the extracted datasheet facts.
What supply voltage ranges are specified for AT24C256?
The recommended operating ranges are 1.8-3.6 V for VCC1, 2.5-5.5 V for VCC2, and 4.5-5.5 V for VCC3. Operating limits depend on the selected voltage option.
What package options are listed for AT24C256?
Listed package options include 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead SAP, and 8-ball dBGA2.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.