Specifications
| Type | Description |
|---|---|
| Part Number | DAC8551 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | DGK VSSOP-8, 3.00 mm x 3.00 mm nominal body |
| Resolution | 16 bits; Static performance; source page 5 |
| Relative Accuracy | ±12 LSB max; DAC8551, measured by line through codes 485 and 64741 at VREF=5 V, codes 970 and 63947 at VREF=2.5 V; source page 5 |
| Relative Accuracy | ±16 LSB max; DAC8551A, measured by line through codes 485 and 64741 at VREF=5 V, codes 970 and 63947 at VREF=2.5 V; source page 5 |
| Differential Nonlinearity | ±1 LSB max; 2.5 V ≤ VREF ≤ 5.5 V, 0°C ≤ TA ≤ 105°C; source page 5 |
| Differential Nonlinearity | ±1 LSB max; 4.2 V < VREF ≤ 5.5 V, -40°C ≤ TA ≤ 105°C; source page 5 |
| Differential Nonlinearity | ±2 LSB max; 2.5 V ≤ VREF ≤ 4.2 V, -40°C ≤ TA ≤ 0°C; source page 5 |
| Zero-Code Error | ±2 mV typ, ±12 mV max; VDD=2.7 V to 5.5 V, -40°C to 105°C; source page 5 |
| Full-Scale Error | ±0.05% FSR typ, ±0.5% FSR max; Measured by line passing through codes 485 and 64741; source page 5 |
| Gain Error | ±0.02% FSR typ, ±0.15% FSR max; DAC8551, measured by line passing through codes 485 and 64741; source page 5 |
| Gain Error | ±0.02% FSR typ, ±0.2% FSR max; DAC8551A, measured by line passing through codes 485 and 64741; source page 5 |
| Zero-Code Error Drift | ±5 µV/°C typ; VDD=2.7 V to 5.5 V, -40°C to 105°C; source page 5 |
| Gain Temperature Coefficient | ±1 ppm of FSR/°C typ; VDD=2.7 V to 5.5 V, -40°C to 105°C; source page 5 |
| Power-Supply Rejection Ratio | 0.75 mV/V typ; RL=2 kΩ, CL=200 pF; source page 5 |
| Output Voltage Range | 0 V to VREF; Voltage output operation; source page 5 |
| Output Voltage Settling Time | 8 µs typ, 10 µs max; To ±0.003% FSR, 0200h to FD00h, RL=2 kΩ, 0 pF < CL < 200 pF; source page 5 |
| Output Voltage Settling Time | 12 µs typ; RL=2 kΩ, CL=50 pF; source page 5 |
| Slew Rate | 1.8 V/µs typ; Output characteristics; source page 5 |
| Capacitive Load Stability | 470 pF typ; RL=∞; source page 5 |
| Capacitive Load Stability | 1000 pF typ; RL=2 kΩ; source page 5 |
| Code Change Glitch Impulse | 0.1 nV-s typ; 1 LSB change around major carry; source page 5 |
| Digital Feedthrough | 0.1 nV-s typ; 50 kΩ series resistance on digital lines; source page 5 |
| DC Output Impedance | 1 Ω typ; At mid-code input; source page 5 |
| Short-Circuit Current | 50 mA typ; VDD=5 V; source page 5 |
| Short-Circuit Current | 20 mA typ; VDD=3 V; source page 5 |
| Power-Up Time | 2.5 µs typ; Coming out of power-down mode, VDD=5 V; source page 5 |
| Power-Up Time | 5 µs typ; Coming out of power-down mode, VDD=3 V; source page 5 |
| Signal-to-Noise Ratio | 95 dB typ; BW=20 kHz, VDD=5 V, fOUT=1 kHz, first 19 harmonics removed for SNR calculation; source page 5 |
| Total Harmonic Distortion | -85 dB typ; BW=20 kHz, VDD=5 V, fOUT=1 kHz, first 19 harmonics removed for SNR calculation; source page 5 |
| Spurious-Free Dynamic Range | 87 dB typ; BW=20 kHz, VDD=5 V, fOUT=1 kHz, first 19 harmonics removed for SNR calculation; source page 5 |
| SINAD | 84 dB typ; BW=20 kHz, VDD=5 V, fOUT=1 kHz, first 19 harmonics removed for SNR calculation; source page 5 |
| Reference Current | 40 µA typ, 75 µA max; VREF=VDD=5 V; source page 5 |
| Reference Current | 30 µA typ, 45 µA max; VREF=VDD=3.6 V; source page 5 |
| Reference Input Range | 0 V to VDD; Reference input; source page 5 |
| Reference Input Impedance | 125 kΩ typ; Reference input; source page 5 |
| Logic Input Current | ±1 µA max; Logic inputs; source page 6 |
| Input Low Voltage | 0.3 x VDD max; 3 V ≤ VDD ≤ 5.5 V; source page 6 |
| Input Low Voltage | 0.1 x VDD max; 2.7 V ≤ VDD < 3 V; source page 6 |
| Input High Voltage | 0.7 x VDD min; 3 V ≤ VDD ≤ 5.5 V; source page 6 |
| Input High Voltage | 0.9 x VDD min; 2.7 V ≤ VDD < 3 V; source page 6 |
| Pin Capacitance | 3 pF typ; Logic inputs; source page 6 |
| Supply Voltage | 2.7 V min, 5.5 V max; Power requirements; source page 6 |
| Supply Current | 160 µA typ, 250 µA max; VDD=3.6 V to 5.5 V, normal mode, input code=32768, no load, excludes reference current, VIH=VDD and VIL=GND; source page 6 |
| Supply Current | 140 µA typ, 240 µA max; VDD=2.7 V to 3.6 V, normal mode, input code=32768, no load, excludes reference current, VIH=VDD and VIL=GND; source page 6 |
| Power-Down Supply Current | 0.2 µA typ, 2 µA max; All power-down modes, VDD=3.6 V to 5.5 V, VIH=VDD and VIL=GND; source page 6 |
| Power-Down Supply Current | 0.05 µA typ, 2 µA max; All power-down modes, VDD=2.7 V to 3.6 V, VIH=VDD and VIL=GND; source page 6 |
| Power Efficiency | 89% typ; ILOAD=2 mA, VDD=5 V; source page 6 |
| Specified Performance Temperature | -40°C to 105°C; Electrical characteristics; source page 6 |
| SCLK Cycle Time | 50 ns min; VDD=2.7 V to 3.6 V; source page 7 |
| SCLK Cycle Time | 33 ns min; VDD=3.6 V to 5.5 V; source page 7 |
| SCLK High Time | 13 ns min; VDD=2.7 V to 3.6 V; source page 7 |
| SCLK Low Time | 22.5 ns min; VDD=2.7 V to 3.6 V; source page 7 |
| Data Setup Time | 5 ns min; VDD=2.7 V to 5.5 V; source page 7 |
| Data Hold Time | 4.5 ns min; VDD=2.7 V to 5.5 V; source page 7 |
| Serial Clock Rate | 30 MHz max; 3-wire serial interface; source page 1 |
| Operating Ambient Temperature | -40°C to 105°C; Recommended operating conditions; source page 4 |
| ESD Rating HBM | ±2000 V; Human-body model per ANSI/ESDA/JEDEC JS-001; source page 4 |
| ESD Rating CDM | ±500 V; Charged-device model per JEDEC JESD22-C101; source page 4 |
| Junction-to-Ambient Thermal Resistance | 206°C/W; DGK VSSOP-8 package; source page 4 |
| Datasheet Status | request_only |
Product Overview
The DAC8551 is a Texas Instruments 16-bit voltage-output DAC for Signal_Chain designs. Its output voltage range is specified from 0 V to VREF, while the reference input range is 0 V to VDD with 125 kΩ typical reference input impedance. Static performance includes ±12 LSB maximum relative accuracy for DAC8551 and ±1 LSB maximum differential nonlinearity across specified VREF and temperature ranges, with a ±2 LSB maximum condition at lower VREF and subzero ambient temperature.
Output behavior is characterized with settling-time, slew-rate, load, and glitch specifications. Settling time is 8 µs typical and 10 µs maximum to ±0.003% FSR for a 0200h-to-FD00h step with RL=2 kΩ and 0 pF < CL < 200 pF. Additional output facts include 1.8 V/µs typical slew rate, 1 Ω typical DC output impedance at mid-code, and 470 pF or 1000 pF typical capacitive-load stability depending on load.
The device is supplied in a DGK VSSOP-8 package with a 3.00 mm x 3.00 mm nominal body. Electrical operation is specified from 2.7 V to 5.5 V and -40°C to 105°C. Digital operation uses a 3-wire serial interface with a 30 MHz maximum serial clock rate, supported by SCLK timing, data setup, and data hold specifications.
Key Features
- 16-bit voltage-output DAC architecture
- 0 V to VREF output voltage range
- 2.7 V to 5.5 V supply range
- 30 MHz maximum 3-wire serial clock rate
- 8 µs typical output settling to ±0.003% FSR
- 1.8 V/µs typical output slew rate
- 0.05 µA typical power-down current at lower supply range
- -40°C to 105°C specified operating ambient range
- DGK VSSOP-8, 3.00 mm x 3.00 mm body
- 95 dB typical SNR at 1 kHz output
Typical Applications
- Precision voltage setpoints
- Signal-chain DAC output stages
- Low-power serial DAC control
- Reference-scaled analog outputs
- Industrial temperature signal paths
- 20 kHz bandwidth waveform outputs
- Microcontroller-controlled voltage outputs
Procurement Notes
When requesting a quote for DAC8551, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What resolution does the DAC8551 provide?
The DAC8551 is specified as a 16-bit voltage-output DAC. Its static performance facts include 16-bit resolution and relative accuracy measured using specified code ranges at VREF values of 5 V and 2.5 V.
What supply voltage range is specified for DAC8551?
The power requirements specify a supply voltage range from 2.7 V minimum to 5.5 V maximum. Supply current is separately specified for 2.7 V to 3.6 V and for 3.6 V to 5.5 V operation.
What package is used for the DAC8551?
The extracted package information lists the DAC8551 in a DGK VSSOP-8 package with a 3.00 mm x 3.00 mm nominal body. The DGK VSSOP-8 package also has a listed junction-to-ambient thermal resistance of 206°C/W.
What serial interface speed is listed for DAC8551?
The device facts specify a 30 MHz maximum serial clock rate for the 3-wire serial interface. Timing facts also include SCLK cycle time, SCLK high and low time, data setup time, and data hold time.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.