Specifications
| Type | Description |
|---|---|
| Part Number | DAC8571 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 8-MSOP (DGK), 3 mm x 5 mm |
| Resolution | 16 bits; VDD=2.7 V to 5.5 V, RL=2 kOhm to GND, CL=200 pF to GND, low power mode, -40°C to 105°C |
| Relative Accuracy | -0.098 % FSR max; static performance, output unloaded, reduced code range 485 to 64714 |
| Differential Nonlinearity | -0.25 typ, -1 max LSB; monotonic by design |
| Offset Error | 0.3 typ, -1.0 max mV; measured at code 485, TA=25°C |
| Offset Error | 1.0 typ, -5.0 max mV; measured at code 485, TA=-40°C to 105°C |
| Full-Scale Error | 0.5 typ, -3.0 max mV; measured at code 64714, TA=25°C |
| Full-Scale Error | 1.0 typ, -5.0 max mV; measured at code 64714, TA=-40°C to 105°C |
| Gain Error | 1.0 typ, -3.0 max mV; measured at code 64714, TA=25°C |
| Gain Error | 2.0 typ, -5.0 max mV; measured at code 64714, TA=-40°C to 105°C |
| Zero-Code Error Drift | -20 µV/°C typ; all zeroes loaded to DAC register |
| Gain Temperature Coefficient | -5 ppm FSR/°C typ; static performance |
| Absolute Accuracy | -2.5 mV typ; all codes from code 485 to code 64714, TA=25°C |
| Absolute Accuracy | -3.5 mV typ; all codes from code 485 to code 64714, TA=-40°C to 105°C |
| Output Voltage Range | 0 V to VREF; output characteristics |
| Full-Scale Output Settling Time | 8 typ, 10 max µs; RL=2 kOhm, CL<200 pF, fast settling |
| Full-Scale Output Settling Time | 12 typ µs; RL=2 kOhm, CL=500 pF, fast settling |
| Full-Scale Output Settling Time | 13 typ, 15 max µs; RL=2 kOhm, CL<200 pF, low power |
| Slew Rate | 1 V/µs typ; RL=2 kOhm, CL<200 pF, fast settling |
| Slew Rate | 0.5 V/µs typ; RL=2 kOhm, CL<200 pF, low power |
| Capacitive Load Stability | 470 pF; RL=infinity |
| Capacitive Load Stability | 1000 pF; RL=2 kOhm |
| Digital-to-Analog Glitch Impulse | 20 nV-s typ; output characteristics |
| Digital Feedthrough | 0.5 nV-s typ; output characteristics |
| DC Output Impedance | 1 Ohm typ; output characteristics |
| Short Circuit Current | 50 mA typ; VDD=5 V |
| Short Circuit Current | 20 mA typ; VDD=3 V |
| Power-Up Time | 2.5 µs typ; coming out of power-down mode, VDD=5 V |
| Power-Up Time | 5 µs typ; coming out of power-down mode, VDD=3 V |
| PSRR | 0.75 mV/V typ; output characteristics |
| Reference Input Range | 0 V to VDD; VREFH input range |
| Reference Input Impedance | 140 kOhm typ; reference input |
| Logic Input Current | -1 µA max; logic inputs |
| Input Low Voltage | 0.3 x VDD max; VDD=2.7 V to 5.5 V |
| Input High Voltage | 0.7 x VDD min; VDD=2.7 V to 5.5 V |
| Pin Capacitance | 3 pF typ; logic inputs |
| Supply Voltage | 2.7 V min, 5.5 V max; power requirements |
| Supply Current, Normal Operation | 250 typ, 400 max µA; VDD=4.5 V to 5.5 V, VIH=VDD, VIL=GND, fast settling, DAC active, reference current included |
| Supply Current, Normal Operation | 160 typ, 225 max µA; VDD=4.5 V to 5.5 V, VIH=VDD, VIL=GND, low power, DAC active, reference current included |
| Supply Current, Normal Operation | 240 typ, 380 max µA; VDD=2.7 V to 3.6 V, VIH=VDD, VIL=GND, fast settling, DAC active, reference current included |
| Supply Current, Normal Operation | 140 typ, 200 max µA; VDD=2.7 V to 3.6 V, VIH=VDD, VIL=GND, low power, DAC active, reference current included |
| Supply Current, Power-Down Modes | 0.2 typ, 1 max µA; VDD=4.5 V to 5.5 V, VIH=VDD and VIL=GND, DAC active, reference current included |
| Supply Current, Power-Down Modes | 0.05 typ, 1 max µA; VDD=2.7 V to 3.6 V, VIH=VDD and VIL=GND, DAC active, reference current included |
| Power Efficiency | 93% typ; IOUT/IDD, IL=2 mA, VDD=5 V |
| I2C SCL Clock Frequency | 100 kHz max; standard mode |
| I2C SCL Clock Frequency | 400 kHz max; fast mode |
| I2C SCL Clock Frequency | 3.4 MHz max; high-speed mode, CB=100 pF max |
| I2C SCL Clock Frequency | 1.7 MHz max; high-speed mode, CB=400 pF max |
| Bus Free Time Between STOP and START | 4.7 µs min; standard mode |
| Bus Free Time Between STOP and START | 1.3 µs min; fast mode |
| START Hold Time | 4.0 µs min; standard mode, repeated START condition |
| START Hold Time | 600 ns min; fast mode, repeated START condition |
| START Hold Time | 160 ns min; high-speed mode, repeated START condition |
| SCL Low Period | 4.7 µs min; standard mode |
| SCL Low Period | 1.3 µs min; fast mode |
| SCL High Period | 4.0 µs min; standard mode |
| SCL High Period | 600 ns min; fast mode |
| SCL High Period | 60 ns min; high-speed mode, CB=100 pF max |
| SCL High Period | 120 ns min; high-speed mode, CB=400 pF max |
| Repeated START Setup Time | 4.7 µs min; standard mode |
| Repeated START Setup Time | 600 ns min; fast mode |
| Repeated START Setup Time | 160 ns min; high-speed mode |
| Data Setup Time | 250 ns min; standard mode |
| Data Setup Time | 100 ns min; fast mode |
| Data Setup Time | 10 ns min; high-speed mode |
| Data Hold Time | 0 min, 0.9 µs max; standard mode |
| Data Hold Time | 0 min, 0.9 µs max; fast mode |
| Data Hold Time | 0 min, 70 ns max; high-speed mode, CB=100 pF max |
| Data Hold Time | 0 min, 150 ns max; high-speed mode, CB=400 pF max |
| SCL Rise Time | 20+0.1CB min, 1000 ns max; standard mode |
| SCL Rise Time | 20+0.1CB min, 300 ns max; fast mode |
| SCL Rise Time | 10 min, 40 ns max; high-speed mode, CB=100 pF max |
| SCL Rise Time | 20 min, 80 ns max; high-speed mode, CB=400 pF max |
| SCL Rise Time After Repeated START/Acknowledge | 20+0.1CB min, 1000 ns max; standard mode |
| SCL Rise Time After Repeated START/Acknowledge | 20+0.1CB min, 300 ns max; fast mode |
| SCL Rise Time After Repeated START/Acknowledge | 10 min, 80 ns max; high-speed mode, CB=100 pF max |
| SCL Rise Time After Repeated START/Acknowledge | 20 min, 160 ns max; high-speed mode, CB=400 pF max |
| SCL Fall Time | 20+0.1CB min, 300 ns max; standard mode |
| SCL Fall Time | 20+0.1CB min, 300 ns max; fast mode |
| SCL Fall Time | 10 min, 40 ns max; high-speed mode, CB=100 pF max |
| SCL Fall Time | 20 min, 80 ns max; high-speed mode, CB=400 pF max |
| SDA Rise Time | 20+0.1CB min, 1000 ns max; standard mode |
| SDA Rise Time | 20+0.1CB min, 300 ns max; fast mode |
| SDA Rise Time | 10 min, 80 ns max; high-speed mode, CB=100 pF max |
| SDA Rise Time | 20 min, 160 ns max; high-speed mode, CB=400 pF max |
| SDA Fall Time | 20+0.1CB min, 300 ns max; standard mode |
| SDA Fall Time | 20+0.1CB min, 300 ns max; fast mode |
| SDA Fall Time | 10 min, 80 ns max; high-speed mode, CB=100 pF max |
| SDA Fall Time | 20 min, 160 ns max; high-speed mode, CB=400 pF max |
| STOP Setup Time | 4.0 µs min; standard mode |
| STOP Setup Time | 600 ns min; fast mode |
| STOP Setup Time | 160 ns min; high-speed mode |
| Capacitive Load for SDA and SCL | 400 pF max; I2C bus timing |
| Suppressed Spike Pulse Width | 50 ns max; fast mode |
| Suppressed Spike Pulse Width | 10 ns max; high-speed mode |
| High-Level Noise Margin | 0.2 x VDD min; each connected device including hysteresis; standard, fast, and high-speed modes |
| Low-Level Noise Margin | 0.1 x VDD min; each connected device including hysteresis; standard, fast, and high-speed modes |
| Operating Temperature Range | -40°C to 105°C; specified temperature range |
| Storage Temperature Range | -65°C to 150°C; absolute maximum ratings |
| Junction Temperature Range | 150°C max; absolute maximum ratings, TJ max |
| Thermal Impedance Junction-to-Ambient | 260°C/W; QJA thermal impedance |
| Thermal Impedance Junction-to-Case | 44°C/W; QJC thermal impedance |
| Analog Supply to GND Absolute Maximum | -0.3 V to 6 V; VDD to GND |
| Digital Input Voltage Absolute Maximum | -0.3 V to VDD+0.3 V; digital input voltage to GND |
| Output Voltage Absolute Maximum | -0.3 V to VDD+0.3 V; VOUT to GND |
| Interface Type | I2C-compatible two-wire serial interface; supports standard, fast, and high-speed modes |
| Output Buffer | On-chip rail-to-rail output buffer; feature description |
| Power-On Reset | Reset to zero output; feature description |
| Datasheet Status | request_only |
Product Overview
The Texas Instruments DAC8571 is a 16-bit voltage output DAC categorized for Signal_Chain functions. It uses an I2C-compatible two-wire serial interface and supports standard, fast, and high-speed bus modes, with SCL clock limits from 100 kHz in standard mode to 3.4 MHz in high-speed mode with 100 pF bus capacitance.
The analog output spans 0 V to VREF and is driven by an on-chip rail-to-rail output buffer. Static and output specifications include monotonic differential nonlinearity by design, 1 Ohm typical DC output impedance, 20 nV-s typical digital-to-analog glitch impulse, and 0.5 nV-s typical digital feedthrough.
The device operates from a 2.7 V to 5.5 V supply over a -40°C to 105°C specified temperature range. It is supplied in an 8-MSOP (DGK), 3 mm x 5 mm package, with thermal impedance values of 260°C/W junction-to-ambient and 44°C/W junction-to-case. Power-on reset sets the output to zero.
Key Features
- 16-bit voltage output DAC resolution
- 0 V to VREF output voltage range
- I2C-compatible two-wire serial interface
- Standard, fast, and high-speed I2C modes
- On-chip rail-to-rail output buffer
- Power-on reset to zero output
- 2.7 V to 5.5 V supply range
- -40°C to 105°C specified operating range
- 8 µs typical fast-settling full-scale output
- 0.05 µA typical power-down current at 3 V
Typical Applications
- I2C-controlled voltage output
- Buffered rail-to-rail DAC output
- Low-power signal-chain control
- High-speed two-wire DAC interface
- Microcontroller-controlled analog output
- Reference-scaled voltage generation
Procurement Notes
When requesting a quote for DAC8571, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of converter is the DAC8571?
The DAC8571 is a Texas Instruments 16-bit voltage output DAC in the Signal_Chain category. Its output range is 0 V to VREF and it includes an on-chip rail-to-rail output buffer.
What interface does the DAC8571 use?
The DAC8571 uses an I2C-compatible two-wire serial interface. The extracted timing specifications cover standard mode at 100 kHz, fast mode at 400 kHz, and high-speed mode up to 3.4 MHz with 100 pF bus capacitance.
What supply voltage range is specified for DAC8571?
The specified supply voltage range is 2.7 V minimum to 5.5 V maximum. Logic thresholds are tied to VDD, with input low voltage at 0.3 x VDD max and input high voltage at 0.7 x VDD min.
What package is listed for the DAC8571?
The listed package is 8-MSOP (DGK), 3 mm x 5 mm. The thermal impedance values provided are 260°C/W junction-to-ambient and 44°C/W junction-to-case.
What happens at DAC8571 power-on reset?
The DAC8571 power-on reset sets the output to zero output. Power-up time from power-down mode is listed as 2.5 µs typical at VDD=5 V and 5 µs typical at VDD=3 V.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.