Specifications
| Type | Description |
|---|---|
| Part Number | DAC8564 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | TSSOP-16, package designator PW |
| Resolution | 16 bits; Static performance |
| Number of DAC Channels | 4 channels; Device description |
| Relative Accuracy | typ ±4 LSB, max ±12 LSB; DAC8564A/DAC8564C, measured by line through codes 485 and 64714 |
| Relative Accuracy | typ ±4 LSB, max ±8 LSB; DAC8564B/DAC8564D, measured by line through codes 485 and 64714 |
| Differential Nonlinearity | typ ±0.5 LSB, max ±1 LSB; 16-bit monotonic |
| Offset Error | typ ±5 mV, max ±8 mV; Static performance |
| Offset Error Drift | typ ±1 µV/°C; Measured by line through codes 485 and 64714 |
| Full-Scale Error | typ ±0.2%, max ±0.5% of FSR; Measured by line through codes 485 and 64714 |
| Gain Error | typ ±0.05%, max ±0.2% of FSR; Static performance |
| Gain Temperature Coefficient | typ ±1 ppm of FSR/°C; AVDD=5 V |
| Gain Temperature Coefficient | typ ±2 ppm of FSR/°C; AVDD=2.7 V |
| Power-Supply Rejection Ratio | typ 1 mV/V; Output unloaded |
| Output Voltage Range | 0 to VREF V; Output characteristics |
| Output Voltage Settling Time | typ 8 µs, max 10 µs; To ±0.003% FSR, 0200h to FD00h, RL=2 kΩ, 0 pF < CL < 200 pF |
| Output Voltage Settling Time | typ 12 µs; RL=2 kΩ, CL=500 pF |
| Slew Rate | typ 2.2 V/µs; Output characteristics |
| Capacitive Load Stability | typ 470 pF; RL=∞ |
| Capacitive Load Stability | typ 1000 pF; RL=2 kΩ |
| Code Change Glitch Impulse | typ 0.15 nV-s; 1 LSB change around major carry |
| Digital Feedthrough | typ 0.15 nV-s; SCLK toggling, SYNC high |
| Channel-to-Channel DC Crosstalk | typ 0.25 LSB; Full-scale swing on adjacent channel |
| Channel-to-Channel AC Crosstalk | typ -100 dB; 1 kHz full-scale sine wave, outputs unloaded |
| DC Output Impedance | typ 1 Ω; At mid-code input |
| Short-Circuit Current | typ 50 mA; Output characteristics |
| Power-Up Time | typ 2.5 µs; Coming out of power-down mode, AVDD=5 V |
| Power-Up Time | typ 5 µs; Coming out of power-down mode, AVDD=3 V |
| SNR | typ 90 dB; TA=25°C, BW=20 kHz, VDD=5 V, fOUT=1 kHz |
| THD | typ -77 dB; TA=25°C, BW=20 kHz, VDD=5 V, fOUT=1 kHz |
| SFDR | typ 78 dB; First 19 harmonics removed for SNR calculation |
| SINAD | typ 77 dB; AC performance |
| DAC Output Noise Density | typ 120 nV/√Hz; TA=25°C, mid-code input, fOUT=1 kHz |
| DAC Output Noise | typ 6 µVPP; TA=25°C, mid-code input, 0.1 Hz to 10 Hz |
| Internal Reference Voltage | 2.5 V; Enabled by default |
| Reference Output Voltage | min 2.4975 V, typ 2.5 V, max 2.5025 V; TA=25°C |
| Reference Initial Accuracy | min -0.1%, typ ±0.004%, max 0.1%; TA=25°C |
| Reference Output Voltage Temperature Drift | typ 5 ppm/°C, max 25 ppm/°C; DAC8564A/DAC8564B |
| Reference Output Voltage Temperature Drift | typ 2 ppm/°C, max 5 ppm/°C; DAC8564C/DAC8564D |
| Reference Output Noise | typ 12 µVPP; f=0.1 Hz to 10 Hz |
| Reference Output Noise Density | typ 50 nV/√Hz; TA=25°C, f=1 MHz, CL=0 µF |
| Reference Output Noise Density | typ 20 nV/√Hz; TA=25°C, f=1 MHz, CL=1 µF |
| Reference Output Noise Density | typ 16 nV/√Hz; TA=25°C, f=1 MHz, CL=4 µF |
| Reference Load Regulation Sourcing | typ 30 µV/mA; TA=25°C |
| Reference Load Regulation Sinking | typ 15 µV/mA; TA=25°C |
| Reference Output Current Load Capability | ±20 mA; Reference output |
| Reference Line Regulation | typ 10 µV/V; TA=25°C |
| Reference Long-Term Stability Drift | typ 50 ppm; TA=25°C, time=0 to 1900 hours |
| Reference Thermal Hysteresis | typ 100 ppm; First cycle |
| Reference Thermal Hysteresis | typ 25 ppm; Additional cycles |
| Internal Reference Current Consumption | typ 360 µA; AVDD=5.5 V |
| Internal Reference Current Consumption | typ 348 µA; AVDD=3.6 V |
| External Reference Current | typ 80 µA; External VREF=2.5 V, internal reference disabled, all four channels active |
| Reference Input Range VREFH | 0 to AVDD V; VREFL < VREFH, AVDD - (VREFH + VREFL)/2 > 1.2 V |
| Reference Input Range VREFL | 0 to AVDD/2 V; VREFL < VREFH, AVDD - (VREFH + VREFL)/2 > 1.2 V |
| Reference Input Impedance | typ 31 kΩ; Reference input |
| AVDD Supply Voltage | min 2.7 V, max 5.5 V; Power requirements |
| IOVDD Supply Voltage | min 1.8 V, max 5.5 V; Power requirements |
| Logic Input Current | max ±1 µA; Logic inputs |
| Logic Input Low Voltage | max 0.3 × IOVDD V; 2.7 V ≤ IOVDD ≤ 5.5 V |
| Logic Input Low Voltage | max 0.1 × IOVDD V; 1.8 V ≤ IOVDD ≤ 2.7 V |
| Logic Input High Voltage | min 0.7 × IOVDD V; 2.7 V ≤ IOVDD ≤ 5.5 V |
| Logic Input High Voltage | min 0.95 × IOVDD V; 1.8 V ≤ IOVDD ≤ 2.7 V |
| Pin Capacitance | typ 3 pF; Logic inputs |
| IOIDD | typ 10 µA, max 20 µA; Power requirements |
| Normal Mode Supply Current | typ 1 mA, max 1.6 mA; AVDD=IOVDD=3.6 V to 5.5 V, VINH=IOVDD and VINL=GND |
| Normal Mode Supply Current | typ 0.95 mA, max 1.5 mA; AVDD=IOVDD=2.7 V to 3.6 V, VINH=IOVDD and VINL=GND |
| Power-Down Supply Current | typ 1.3 µA, max 3.5 µA; All power-down modes, AVDD=IOVDD=3.6 V to 5.5 V, VINH=IOVDD and VINL=GND |
| Power-Down Supply Current | typ 0.5 µA, max 2.5 µA; All power-down modes, AVDD=IOVDD=2.7 V to 3.6 V, VINH=IOVDD and VINL=GND |
| Normal Mode Power Dissipation | typ 3.6 mW, max 8.8 mW; AVDD=IOVDD=3.6 V to 5.5 V, VINH=IOVDD and VINL=GND |
| Normal Mode Power Dissipation | typ 2.6 mW, max 5.4 mW; AVDD=IOVDD=2.7 V to 3.6 V, VINH=IOVDD and VINL=GND |
| Power-Down Power Dissipation | typ 4.7 µW, max 19 µW; All power-down modes, AVDD=IOVDD=3.6 V to 5.5 V, VINH=IOVDD and VINL=GND |
| Power-Down Power Dissipation | typ 1.4 µW, max 9 µW; All power-down modes, AVDD=IOVDD=2.7 V to 3.6 V, VINH=IOVDD and VINL=GND |
| Specified Temperature Range | -40°C to +105°C; Specified performance |
| Operating Temperature Range | -40°C to +125°C; Absolute maximum ratings |
| Storage Temperature Range | -65°C to +150°C; Absolute maximum ratings |
| Junction Temperature Range | max +150°C; Absolute maximum ratings, TJ max |
| Thermal Impedance JA | +118°C/W; TSSOP-16 package |
| Thermal Impedance JC | +29°C/W; TSSOP-16 package |
| ESD Rating HBM | 4000 V; Human body model |
| ESD Rating CDM | 1500 V; Charged device model |
| Serial Interface Maximum Clock Rate | up to 50 MHz; 3-wire serial interface; compatible with SPI, QSPI, Microwire, DSP interfaces |
| Maximum SCLK Frequency | 50 MHz; IOVDD=AVDD=3.6 V to 5.5 V |
| Maximum SCLK Frequency | 25 MHz; IOVDD=AVDD=2.7 V to 3.6 V |
| SCLK Cycle Time | min 40 ns; IOVDD=AVDD=2.7 V to 3.6 V |
| SCLK Cycle Time | min 20 ns; IOVDD=AVDD=3.6 V to 5.5 V |
| SCLK High Time | min 20 ns; IOVDD=AVDD=2.7 V to 3.6 V |
| SCLK High Time | min 10 ns; IOVDD=AVDD=3.6 V to 5.5 V |
| SCLK Low Time | min 20 ns; IOVDD=AVDD=2.7 V to 3.6 V |
| SCLK Low Time | min 10 ns; IOVDD=AVDD=3.6 V to 5.5 V |
| Data Setup Time | min 5 ns; Timing requirement t5 |
| Data Hold Time | min 4.5 ns; Timing requirement t6 |
| Minimum SYNC High Time | min 40 ns; IOVDD=AVDD=2.7 V to 3.6 V |
| Minimum SYNC High Time | min 20 ns; IOVDD=AVDD=3.6 V to 5.5 V |
| Power-On Reset Output State | zero-scale; DAC output powers up at zero-scale and remains until valid code is written |
| Datasheet Status | request_only |
Product Overview
The DAC8564 is a Texas Instruments 16-bit quad voltage-output DAC for Signal_Chain designs requiring four independent analog output channels. Its static performance includes 16-bit resolution, 16-bit monotonic differential nonlinearity of typical ±0.5 LSB and maximum ±1 LSB, and relative accuracy options of typical ±4 LSB with maximum ±12 LSB for DAC8564A/DAC8564C or maximum ±8 LSB for DAC8564B/DAC8564D.
The device provides a 0 to VREF V output range, a 2.5 V internal reference enabled by default, and reference output accuracy from 2.4975 V to 2.5025 V at TA = 25°C. Reference drift depends on grade, with DAC8564A/DAC8564B specified at typical 5 ppm/°C and maximum 25 ppm/°C, and DAC8564C/DAC8564D at typical 2 ppm/°C and maximum 5 ppm/°C.
Digital control uses a 3-wire serial interface compatible with SPI, QSPI, Microwire, and DSP interfaces. Maximum SCLK is 50 MHz for IOVDD = AVDD = 3.6 V to 5.5 V and 25 MHz for 2.7 V to 3.6 V. The package is TSSOP-16, package designator PW, with specified performance from -40°C to +105°C.
Key Features
- 16-bit resolution with four voltage-output DAC channels
- Relative accuracy to max ±8 LSB on B/D grades
- 16-bit monotonic DNL, max ±1 LSB
- Output range from 0 to VREF V
- Typical 8 µs settling to ±0.003% FSR
- 2.5 V internal reference enabled by default
- AVDD range from 2.7 V to 5.5 V
- IOVDD range from 1.8 V to 5.5 V
- SPI, QSPI, Microwire, and DSP-compatible 3-wire interface
- Up to 50 MHz serial clock at higher supply range
- Zero-scale power-on reset output state
- TSSOP-16 package, designator PW
Typical Applications
- Quad voltage-output generation
- SPI-controlled analog outputs
- DSP-controlled signal-chain outputs
- Reference-based DAC output stages
- Low-power power-down signal paths
- 1 kHz AC performance evaluation
- Multi-channel DC output control
- TSSOP-16 board assemblies
Procurement Notes
When requesting a quote for DAC8564, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
How many DAC channels does the DAC8564 include?
The DAC8564 includes four DAC channels. The extracted device description identifies it as a 16-bit quad voltage-output DAC, so each device provides four voltage-output DAC outputs.
What supply voltage ranges does DAC8564 support?
The AVDD supply voltage range is 2.7 V to 5.5 V, while the IOVDD supply voltage range is 1.8 V to 5.5 V. Timing limits differ between the 2.7 V to 3.6 V and 3.6 V to 5.5 V ranges.
What serial interface timing is specified for DAC8564?
The device uses a 3-wire serial interface compatible with SPI, QSPI, Microwire, and DSP interfaces. Maximum SCLK is 50 MHz for IOVDD=AVDD=3.6 V to 5.5 V and 25 MHz for 2.7 V to 3.6 V.
What reference is integrated in the DAC8564?
The DAC8564 includes a 2.5 V internal reference enabled by default. At TA=25°C, reference output voltage is specified from 2.4975 V minimum to 2.5025 V maximum, with a typical value of 2.5 V.
What output state occurs after power-on reset?
The DAC8564 output powers up at zero-scale and remains at zero-scale until a valid code is written. This power-on reset behavior is included in the extracted device description.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.