Specifications
| Type | Description |
|---|---|
| Part Number | DRV8305 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Package / Case | 48-pin HTQFP, PHP package, 7.00 mm x 7.00 mm body |
| Operating Supply Voltage | 4.4 to 45 V; recommended operating conditions, PVDD |
| Voltage Regulator Supply Voltage | 4.3 to 45 V; recommended operating conditions for voltage regulator operation |
| Peak Gate Drive Current | 1.25 A and 1 A; feature summary |
| Gate Driver Switching Frequency | up to 200 kHz; 3-PWM or 6-PWM input control |
| Recommended Gate Driver Switching Frequency | 200 kHz max; recommended operating conditions, Fgate |
| Integrated LDO Output Current | 50 mA; integrated LDO option, 3.3 V or 5 V |
| LDO Output Options | 3.3 V or 5 V; DRV83053 provides 3.3-V LDO; DRV83055 provides 5-V LDO |
| Current Shunt Amplifiers | 3 integrated bidirectional amplifiers; low-side current measurements with variable gain and adjustable offset reference |
| PWM Input Modes | 3-PWM, 6-PWM, and single-PWM mode; input control and commutation capability |
| Digital Interface Compatibility | 3.3 V and 5 V; digital interface support |
| Configuration Interface | SPI; device settings, diagnostics, and fault reporting |
| Absolute Maximum PVDD Voltage | -0.3 to 45 V; referenced to GND |
| Absolute Maximum PVDD Ramp Rate | 0 to 2 V/us |
| Absolute Maximum Charge Pump Voltage | -0.3 V to PVDD + 12 V; CP1H, CP1L, CP2L, CP2H, VCPH, VCP_LSD |
| Absolute Maximum High-Side Gate Driver Voltage | -3 to 57 V; GHA, GHB, GHC |
| Absolute Maximum Low-Side Gate Driver Voltage | -2 to 12 V |
| Absolute Maximum High-Side Source Pin Voltage | -5 to 45 V; SHA, SHB, SHC |
| Absolute Maximum Low-Side Source Pin Voltage | -3 to 5 V; SLA, SLB, SLC |
| Absolute Maximum VDRAIN Voltage | -0.3 to 45 V; drain pin voltage |
| Absolute Maximum VDRAIN Source Current | -20 mA; limit current with external series resistor |
| Absolute Maximum VDRAIN Sink Current | 2 mA |
| Absolute Maximum PVDD to VDRAIN Difference | -10 to 10 V; PVDD - VDRAIN |
| Control Pin Voltage Range | -0.3 to 5.5 V; INHA, INLA, INHB, INLB, INHC, INLC, EN_GATE, SCLK, SDI, SCS, SDO, nFAULT, PWRGD |
| Open-Drain Pin Sink Current | 7 mA; nFAULT and PWRGD |
| WAKE Pin Voltage | -0.3 to 45 V |
| WAKE Pin Sink Current | 1 mA; limit with external series resistor |
| Sense Amplifier Input Voltage | -2 to 5 V; sense amplifier pins |
| External Reference Voltage | -0.3 to 5.5 V; VREG when vreg_vref = 1 |
| External Reference Sink Current | 100 uA; VREG when vreg_vref = 1 |
| Operating Ambient Temperature | -40 to 125 degC; absolute maximum ratings and recommended operating conditions |
| Operating Junction Temperature | -40 to 150 degC; absolute maximum ratings |
| Storage Temperature | -55 to 150 degC; absolute maximum ratings |
| ESD Rating HBM | +/-2000 V; human-body model per ANSI/ESDA/JEDEC JS-001 |
| ESD Rating CDM | +/-500 V; charged-device model per JEDEC JESD22-C101 |
| PVDD Ramp Rate | 1 V/us max; PVDD = 0 to 20 V rising, less than 3 mA pin sink current |
| Total Voltage Drop PVDD to SH_X | 4.5 V max; recommended operating conditions |
| External Load on VCPH Pin | 10 mA max; current-limit resistor in series to load |
| Shunt Amplifier Capacitive Load | 60 pF max; no external resistor on output, excluding internal pin capacitance |
| nFAULT Sink Current | 7 mA max; VnFAULT = 0.3 V |
| Total Average Gate Driver Current | 30 mA max; HS + LS, charge-pump limited |
| Junction-to-Ambient Thermal Resistance | 26.6 degC/W; PHP HTQFP 48-pin package |
| Junction-to-Case Top Thermal Resistance | 12.9 degC/W; PHP HTQFP 48-pin package |
| Junction-to-Board Thermal Resistance | 7 degC/W; PHP HTQFP 48-pin package; value truncated in provided content |
| PVDD Bypass Capacitor | 4.7 uF ceramic; rated for PVDD |
| AVDD Bypass Capacitor | 1 uF ceramic; rated for 6.3 V |
| DVDD Bypass Capacitor | 1 uF ceramic; rated for 6.3 V |
| VCPH Capacitor | 2.2 uF ceramic; between VCPH and PVDD, rated for 16 V |
| VCP_LSD Capacitor | 1 uF ceramic; between VCP_LSD and GND, rated for 16 V |
| Charge Pump CP1 Capacitor | 0.047 uF ceramic; between CP1H and CP1L, rated for PVDD |
| Charge Pump CP2 Capacitor | 0.047 uF ceramic; between CP2H and CP2L, rated for PVDD x 2 |
| VREG Capacitor | 1 uF ceramic; between VREG and GND, rated for 6.3 V |
| VDRAIN Series Resistor | 100 ohm; between VDRAIN and high-side MOSFET drain |
| nFAULT Pullup Resistor | 1 to 10 kohm; pulled up to MCU power supply |
| PWRGD Pullup Resistor | 1 to 10 kohm; pulled up to MCU power supply |
| Datasheet Status | request_only |
Product Overview
The DRV8305 is a Texas Instruments three-phase gate driver for Power_Management designs using external power MOSFET stages. It operates from a recommended PVDD range of 4.4 to 45 V, with voltage regulator operation specified from 4.3 to 45 V. The gate driver supports 3-PWM, 6-PWM, and single-PWM input control, with gate-driver switching specified up to 200 kHz and a recommended Fgate maximum of 200 kHz.
Integrated functions include three bidirectional current shunt amplifiers for low-side current measurements with variable gain and adjustable offset reference. The device also provides SPI access for settings, diagnostics, and fault reporting, plus 3.3 V and 5 V digital interface compatibility. LDO variants provide either 3.3 V or 5 V output at 50 mA.
The package is a 48-pin HTQFP PHP package with a 7.00 mm x 7.00 mm body. Recommended external components include PVDD, AVDD, DVDD, VCPH, VCP_LSD, charge-pump, and VREG capacitors, plus VDRAIN series and nFAULT/PWRGD pullup resistors.
Key Features
- 4.4 to 45 V recommended PVDD operating range
- 4.3 to 45 V voltage regulator supply range
- 1.25 A and 1 A peak gate drive current
- Gate driver switching frequency up to 200 kHz
- 3-PWM, 6-PWM, and single-PWM input modes
- Three integrated bidirectional low-side current shunt amplifiers
- SPI configuration, diagnostics, and fault reporting interface
- 3.3 V and 5 V digital interface compatibility
- Integrated 3.3 V or 5 V LDO options
- 50 mA integrated LDO output current
- -40 to 125 degC operating ambient range
- 48-pin HTQFP PHP package, 7.00 mm square body
Typical Applications
- Three-phase motor gate driving
- External MOSFET bridge control
- Low-side current measurement systems
- SPI-configured power stages
- 3-PWM motor control designs
- 6-PWM motor control designs
- Single-PWM commutation designs
- MCU-interfaced motor drives
Procurement Notes
When requesting a quote for DRV8305, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What supply voltage range does the DRV8305 support?
The DRV8305 recommended PVDD operating supply range is 4.4 to 45 V. Its voltage regulator operation is specified for a 4.3 to 45 V supply range under the extracted recommended operating conditions.
Which PWM input modes are available on the DRV8305?
The device supports 3-PWM, 6-PWM, and single-PWM modes for input control and commutation capability. The extracted facts also specify gate-driver switching up to 200 kHz for 3-PWM or 6-PWM input control.
Does the DRV8305 include current shunt amplifiers?
Yes. The DRV8305 includes three integrated bidirectional current shunt amplifiers intended for low-side current measurements, with variable gain and an adjustable offset reference according to the extracted datasheet facts.
What package is specified for the DRV8305?
The listed package is a 48-pin HTQFP PHP package with a 7.00 mm x 7.00 mm body. Thermal data includes 26.6 degC/W junction-to-ambient and 12.9 degC/W junction-to-case top resistance.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.