Specifications
| Type | Description |
|---|---|
| Part Number | LMK1C1102 |
| Manufacturer | Texas Instruments |
| Product Type | LVCMOS Clock Buffer |
| Category | Signal Chain |
| Number of Outputs | 2 |
| Clock Buffer Fanout | 1:2 |
| Supported Supply Voltages | 1.8 V, 2.5 V, 3.3 V |
| 3.3-V Supply Voltage Range | 3.135-3.465 V |
| 2.5-V Supply Voltage Range | 2.375-2.625 V |
| 1.8-V Supply Voltage Range | 1.71-1.89 V |
| Operating Free-Air Temperature | -40 to 125 °C |
| Operating Junction Temperature | -40 to 150 °C |
| Supply Voltage Absolute Maximum | -0.5 to 3.6 V |
| CLKIN Input Voltage Absolute Maximum | -0.5 to 3.6 V |
| Output Pin Voltage Absolute Maximum | -0.5 to VDD + 0.3 V |
| Input Current Absolute Maximum | -20 to 20 mA |
| Continuous Output Current Absolute Maximum | -50 to 50 mA |
| Storage Temperature | -65 to 150 °C |
| HBM ESD Rating | ±9000 V |
| CDM ESD Rating | ±1500 V |
| Static Core Supply Current | 25 µA typ, 45 µA max |
| Core Supply Current | 8 mA typ, 15 mA max |
| Core Supply Current | 14 mA typ, 20 mA max |
| Core Supply Current | 21 mA typ, 30 mA max |
| Core Supply Current | 33 mA typ, 40 mA max |
| Input Frequency | DC to 250 MHz |
| Input Frequency | DC to 200 MHz |
| Input High Voltage | 0.7 x VDD min |
| Input Low Voltage | 0.3 x VDD max |
| Input Slew Rate | 0.1 V/ns min |
| Input Leakage Current | -50 to 50 µA |
| Input Capacitance | 7 pF typ |
| Output Frequency | 250 MHz max |
| Output Frequency | 200 MHz max |
| Output Duty Cycle | 45%-55% |
| Start-Up Time Before Output Active | 3 ms max |
| Output Enable Time | 5 cycles max |
| Output Disable Time | 5 cycles max |
| Output High Voltage | 2.8 V min |
| Output Low Voltage | 0.2 V max |
| Output Rise and Fall Time | 0.35 ns typ, 0.7 ns max |
| Output-to-Output Skew | 25 ps typ, 50 ps max |
| Part-to-Part Skew | 250 ps max |
| Propagation Delay | 1.5 ns typ, 2 ns max |
| Additive Jitter | 8 fs RMS typ, 20 fs RMS max |
| Output Impedance | 50 Ω typ |
| Output High Voltage | 0.8 x VDD min |
| Output Low Voltage | 0.2 x VDD max |
| Output Rise and Fall Time | 0.33 ns typ, 0.8 ns max |
| Output-to-Output Skew | 50 ps max |
| Part-to-Part Skew | 400 ps max |
| Propagation Delay | 1.5 ns typ, 2.5 ns max |
| Additive Jitter | 11 fs RMS typ, 27 fs RMS max |
| Output Impedance | 52.5 Ω typ |
| Output High Voltage | 0.8 x VDD min |
| Output Low Voltage | 0.2 x VDD max |
| Output Rise and Fall Time | 0.38 ns typ, 1 ns max |
| CLKIN Pin | Pin 1 |
| 1G Output Enable Pin | Pin 2 |
| Y0 Output Pin | Pin 3 |
| Y1 Output Pin | Pin 8 |
| VDD Pin | Pin 6 |
| GND Pin | Pin 4 |
| Internal Pulldown Resistance | 300 kΩ typ |
| Recommended Decoupling Capacitor | 0.1 µF |
| Input Tolerance | 3.3-V tolerant input |
| Fail-Safe Input | Supported |
| Datasheet Status | request_only |
Product Overview
The LMK1C1102 is a Texas Instruments LVCMOS clock buffer in the Signal_Chain category. The device variant provides a 1:2 fanout with two outputs, Y0 and Y1, from a CLKIN input. A 1G enable pin controls the outputs, with HIGH enabling outputs and LOW disabling them.
Key Features
- Two-output LVCMOS clock buffer device variant
- 1:2 clock buffer fanout from CLKIN
- Supports 1.8 V, 2.5 V, and 3.3 V supplies
- DC to 250 MHz input frequency at 3.3 V
- DC to 200 MHz input frequency at 2.5 V or 1.8 V
- 45%-55% output duty cycle with 50% duty input
- 8 fs RMS typical additive jitter at 3.3 V
- 1G pin enables and disables both outputs
- 3.3-V tolerant input at all supply voltages
- Fail-safe input prevents output oscillation without input signal
Typical Applications
- LVCMOS clock fanout
- Two-output clock distribution
- Multi-supply clock buffering
- Enable-controlled clock outputs
- Low-jitter clock trees
- Fail-safe clock input interfaces
- Compact TSSOP or WSON assemblies
Procurement Notes
When requesting a quote for LMK1C1102, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
How many outputs does the LMK1C1102 provide?
The LMK1C1102 device variant provides two LVCMOS outputs. Its clock buffer fanout is specified as 1:2, using the CLKIN input and the Y0 and Y1 output pins.
Which supply voltages are supported by LMK1C1102?
The nominal operating supplies are 1.8 V, 2.5 V, and 3.3 V. Recommended ranges are 1.71-1.89 V, 2.375-2.625 V, and 3.135-3.465 V respectively.
What maximum clock frequency does LMK1C1102 support?
At VDD = 3.3 V, the input frequency range is DC to 250 MHz and the output frequency maximum is 250 MHz. At 2.5 V or 1.8 V, both input and output frequency ratings are up to 200 MHz.
What packages are listed for the LMK1C1102?
The listed package options are 8-pin TSSOP (PW), measuring 3.00 mm x 4.40 mm, and 8-pin WSON (DQF), measuring 2.00 mm x 2.00 mm.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.