Specifications
| Type | Description |
|---|---|
| Part Number | MSP430FR5949 |
| Manufacturer | Texas Instruments |
| Product Type | 16-bit FRAM microcontroller |
| Category | MCU & Processors |
| Component Type | MCU |
| Package / Case | VQFN(40) RHA 6 mm x 6 mm; TSSOP(38) DA 12.5 mm x 6.2 mm |
| CPU Architecture | 16-bit RISC; condition: MSP430 CPU |
| Maximum Clock Frequency | up to 16 MHz; condition: 16-bit RISC architecture |
| Supply Voltage Range | 1.8 V to 3.6 V; condition: minimum supply voltage restricted by SVS levels |
| Active Mode Current | approximately 100 uA/MHz; condition: Active mode |
| Standby Current | 0.4 uA typical; condition: LPM3 with VLO |
| Real-Time Clock Current | 0.25 uA typical; condition: LPM3.5, RTC clocked by 3.7-pF crystal |
| Shutdown Current | 0.02 uA typical; condition: LPM4.5 |
| FRAM Size | 64 KB; condition: MSP430FR5949 device variant |
| SRAM Size | 2 KB; condition: MSP430FR5949 device variant |
| FRAM Write Speed | 125 ns per word; 64 KB in 4 ms; condition: Fast write operation |
| FRAM Endurance | 10^15 write cycles; condition: Nonvolatile FRAM memory |
| Memory Architecture | Unified memory; condition: Program, data, and storage in one address space |
| Clock System | DCO, LFXT; condition: MSP430FR5949 device variant |
| DCO Frequencies | 10 selectable factory-trimmed frequencies; condition: Fixed-frequency DCO |
| ADC Resolution | 12-bit; condition: ADC12_B with internal reference and sample-and-hold |
| ADC Channels | 14 external, 2 internal channels; condition: MSP430FR5949 in 40RHA package |
| ADC Channels | 12 external, 2 internal channels; condition: MSP430FR5949 in 38DA package |
| Analog Comparator Channels | 16 channels; condition: Comp_E comparator |
| DMA | 3 channels; condition: Internal DMA controller |
| Hardware Multiplier | 32-bit; condition: MPY peripheral |
| Timer_A Instances | 3,3 and 2,2 capture/compare registers; condition: MSP430FR5949 device variant; TA0 and TA1 support internal/external capture/PWM, TA2 and TA3 internal only |
| Timer_B | 7 capture/compare registers; condition: MSP430FR5949 device variant |
| Serial Interfaces | 2 eUSCI_A, 1 eUSCI_B; condition: MSP430FR5949 device variant |
| eUSCI_A Functions | UART with automatic baud-rate detection, IrDA encode/decode, SPI; condition: eUSCI_A0 and eUSCI_A1 |
| eUSCI_B Functions | I2C with multiple slave addressing, SPI; condition: eUSCI_B0 |
| AES Security | 128-bit or 256-bit AES encryption and decryption coprocessor; condition: MSP430FR5949 AES listed as yes |
| Bootloader Interface | UART; condition: MSP430FR5949 BSL |
| I/O Count | 33 I/O; condition: MSP430FR5949 in 40RHA package |
| I/O Count | 31 I/O; condition: MSP430FR5949 in 38DA package |
| Capacitive Touch Support | All pins support capacitive touch capability; condition: No external components required |
| Datasheet Status | request_only |
Product Overview
The MSP430FR5949 is a Texas Instruments 16-bit FRAM microcontroller built around the MSP430 16-bit RISC CPU. The device operates up to 16 MHz and supports a 1.8 V to 3.6 V supply range, with the minimum supply voltage restricted by SVS levels. Current figures include approximately 100 uA/MHz in active mode, 0.4 uA typical in LPM3 with VLO, 0.25 uA typical in LPM3.5 with RTC clocked by a 3.7-pF crystal, and 0.02 uA typical in LPM4.5.
Memory resources include 64 KB FRAM and 2 KB SRAM with a unified memory architecture for program, data, and storage in one address space. The FRAM supports 125 ns per word writes, 64 KB writes in 4 ms, and 10^15 write cycles.
Peripheral resources include a 12-bit ADC12_B, Comp_E comparator, 3-channel DMA, 32-bit hardware multiplier, Timer_A and Timer_B blocks, 2 eUSCI_A interfaces, 1 eUSCI_B interface, and a 128-bit or 256-bit AES encryption and decryption coprocessor. Package-dependent resources include 33 I/O and 14 external ADC channels in the 40RHA package, or 31 I/O and 12 external ADC channels in the 38DA package.
Key Features
- 16-bit MSP430 RISC CPU up to 16 MHz
- 1.8 V to 3.6 V supply voltage range
- 64 KB FRAM and 2 KB SRAM memory
- Unified program, data, and storage address space
- FRAM writes at 125 ns per word
- FRAM endurance rated for 10^15 write cycles
- 12-bit ADC12_B with internal reference
- 3-channel internal DMA controller
- 128-bit or 256-bit AES coprocessor
- UART, IrDA, SPI, and I2C interface support
- All pins support capacitive touch capability
Typical Applications
- Low-power sensing nodes
- FRAM data logging
- Capacitive touch interfaces
- Secure embedded control
- UART bootloader-based designs
- SPI and I2C connected modules
- Timer-based PWM control
- RTC-enabled low-power systems
Procurement Notes
When requesting a quote for MSP430FR5949, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What CPU core does the MSP430FR5949 use?
The MSP430FR5949 uses the MSP430 16-bit RISC CPU architecture. The extracted datasheet facts specify operation up to 16 MHz for this 16-bit RISC architecture.
How much memory is available on MSP430FR5949?
The MSP430FR5949 device variant includes 64 KB of FRAM and 2 KB of SRAM. Its unified memory architecture places program, data, and storage in one address space.
Which serial interfaces are included on MSP430FR5949?
The device includes 2 eUSCI_A interfaces and 1 eUSCI_B interface. eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI. eUSCI_B supports I2C with multiple slave addressing and SPI.
How do package options affect I/O and ADC channels?
In the 40RHA package, MSP430FR5949 provides 33 I/O and 14 external plus 2 internal ADC channels. In the 38DA package, it provides 31 I/O and 12 external plus 2 internal ADC channels.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.