Specifications
| Type | Description |
|---|---|
| Part Number | SN74AVC8T245 |
| Manufacturer | Texas Instruments |
| Product Type | Level Shifter |
| Category | Logic |
| Package/Case | RHL (VQFN, 24) 5.5 mm x 3.5 mm; PW (TSSOP, 24) 7.8 mm x 6.4 mm; DGV (TVSOP, 24) 5 mm x 6.4 mm |
| Function | 8-bit noninverting bus transceiver with configurable voltage translation and 3-state outputs |
| Supply Rails | Dual configurable power-supply rails: VCCA and VCCB |
| Recommended VCCA Supply Voltage | 1.2 V to 3.6 V |
| Recommended VCCB Supply Voltage | 1.2 V to 3.6 V |
| Optimized Operating Supply Range | 1.4 V to 3.6 V |
| Low-Voltage Operation | Operational with VCCA and VCCB as low as 1.2 V |
| Supported Translation Nodes | 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V |
| Control Pin Supply Reference | DIR and OE supplied/referenced by VCCA |
| Direction Control | DIR low/high controls A-to-B or B-to-A data transmission |
| Output Enable | OE disables outputs to isolate buses; pull OE high for 3-state mode |
| VCC Isolation Feature | All I/O ports high-impedance if either VCC input is at GND |
| Partial Power-Down Support | Ioff circuitry disables outputs to prevent damaging current backflow |
| I/O Tolerance | I/Os are 4.6-V tolerant |
| Maximum Data Rate | 170 Mbps when VCCA < 1.8 V or VCCB < 1.8 V |
| Maximum Data Rate | 320 Mbps when VCCA >= 1.8 V and VCCB >= 1.8 V |
| Absolute Maximum Supply Voltage | -0.5 V to 4.6 V for VCCA and VCCB |
| Absolute Maximum Input Voltage | -0.5 V to 4.6 V for I/O ports A/B and control inputs |
| Absolute Maximum Output Voltage, High-Impedance or Power-Off | -0.5 V to 4.6 V for A port or B port |
| Absolute Maximum Output Voltage, Active High/Low State | A port: -0.5 V to VCCA + 0.5 V; B port: -0.5 V to VCCB + 0.5 V |
| Input Clamp Current | -50 mA when VI < 0 V |
| Output Clamp Current | -50 mA when VO < 0 V |
| Continuous Output Current | -50 mA to 50 mA |
| Continuous Current Through Supply or Ground | -100 mA to 100 mA through VCCA, VCCB, or GND |
| Storage Temperature Range | -65°C to 150°C |
| Operating Free-Air Temperature Range | -40°C to 125°C |
| ESD Rating HBM | ±8000 V, human-body model per ANSI/ESDA/JEDEC JS-001; feature list references JESD 22 A114-A |
| ESD Rating CDM | ±1000 V, charged-device model per JEDEC JESD22-C101 |
| ESD Rating MM | ±200 V, machine model; feature list references JESD 22 A115-A |
| Latch-Up Performance | Exceeds 100 mA per JESD 78, Class II |
| High-Level Input Voltage, Data Inputs | VCCI x 0.65 minimum when VCCI = 1.2 V to 1.95 V |
| High-Level Input Voltage, Data Inputs | 1.6 V minimum when VCCI = 1.95 V to 2.7 V |
| High-Level Input Voltage, Data Inputs | 2 V minimum when VCCI = 2.7 V to 3.6 V |
| Low-Level Input Voltage, Data Inputs | VCCI x 0.35 maximum when VCCI = 1.2 V to 1.95 V |
| Low-Level Input Voltage, Data Inputs | 0.7 V maximum when VCCI = 1.95 V to 2.7 V |
| Low-Level Input Voltage, Data Inputs | 0.8 V maximum when VCCI = 2.7 V to 3.6 V |
| High-Level DIR Input Voltage | VCCA x 0.65 minimum; 1.6 V minimum; 2 V minimum for VCCA ranges 1.2 V to 1.95 V; 1.95 V to 2.7 V; 2.7 V to 3.6 V |
| Low-Level DIR Input Voltage | VCCA x 0.35 maximum; 0.7 V maximum; 0.8 V maximum for VCCA ranges 1.2 V to 1.95 V; 1.95 V to 2.7 V; 2.7 V to 3.6 V |
| Input Voltage Range | 0 V to 3.6 V |
| Output Voltage Range | Active state: 0 V to VCCO; 3-state: 0 V to 3.6 V |
| High-Level Output Current | -3 mA, -6 mA, -8 mA, -9 mA, -12 mA for VCCO = 1.2 V; 1.4 V to 1.6 V; 1.65 V to 1.95 V; 2.3 V to 2.7 V; 3 V to 3.6 V |
| Low-Level Output Current | 3 mA, 6 mA, 8 mA, 9 mA, 12 mA for VCCO = 1.2 V; 1.4 V to 1.6 V; 1.65 V to 1.95 V; 2.3 V to 2.7 V; 3 V to 3.6 V |
| Input Transition Rise or Fall Rate | 5 ns/V maximum |
| VOH | VCCO - 0.2 V minimum at IOH = -100 µA, VCCA = 1.2 V to 3.6 V, VCCB = 1.2 V to 3.6 V |
| VOH | 0.95 V minimum at IOH = -3 mA, VI = VIH, VCCA = VCCB = 1.2 V, TA = 25°C |
| VOH | 1.05 V typical, 1 V minimum at IOH = -6 mA, VI = VIH, VCCA = VCCB = 1.4 V |
| VOH | 1.2 V minimum at IOH = -8 mA, VI = VIH, VCCA = VCCB = 1.65 V |
| VOH | 1.75 V minimum at IOH = -9 mA, VI = VIH, VCCA = VCCB = 2.3 V |
| VOH | 2.3 V minimum at IOH = -12 mA, VI = VIH, VCCA = VCCB = 3 V |
| VOL | 0.2 V maximum at IOL = 100 µA, VCCA = 1.2 V to 3.6 V, VCCB = 1.2 V to 3.6 V |
| VOL | 0.15 V typical at IOL = 3 mA, VI = VIL, VCCA = VCCB = 1.2 V, TA = 25°C |
| VOL | 0.35 V maximum at IOL = 6 mA, VI = VIL, VCCA = VCCB = 1.4 V |
| VOL | 0.45 V maximum at IOL = 8 mA, VI = VIL, VCCA = VCCB = 1.65 V |
| VOL | 0.55 V maximum at IOL = 9 mA, VI = VIL, VCCA = VCCB = 2.3 V |
| VOL | 0.7 V maximum at IOL = 12 mA, VI = VIL, VCCA = VCCB = 3 V |
| Control Input Leakage Current | -0.25 µA min, ±0.025 µA typical, 0.25 µA max at 25°C; -1 µA to 1 µA over temperature |
| Ioff Leakage, A or B Port | -1 µA to 1 µA at 25°C; -5 µA to 5 µA over temperature with one supply at 0 V |
| 3-State Output Leakage Current IOZ | ±0.5 µA typical, ±2.5 µA max at 25°C; ±5 µA max over temperature |
| ICCA | 15 µA maximum |
| ICCB | 15 µA maximum |
| Total Supply Current ICCA + ICCB | 25 µA maximum |
| Control Input Capacitance | 3.5 pF typical, 4.5 pF maximum |
| I/O Port Capacitance | 6 pF typical, 7 pF maximum |
| Thermal Resistance RthetaJA | DGV: 116.7°C/W; PW: 93.1°C/W; RHL: 36.8°C/W |
| Thermal Resistance RthetaJC(top) | DGV: 48.5°C/W; PW: 36.7°C/W; RHL: 32.5°C/W |
| Thermal Resistance RthetaJB | DGV: 62.1°C/W; PW: 48.4°C/W; RHL: 15.7°C/W |
| Thermal Resistance RthetaJC(bottom) | RHL: 5.6°C/W; DGV/PW: N/A |
| Propagation Delay A to B at VCCA = 1.2 V | 3.1 ns, 2.6 ns, 2.5 ns, 3 ns, 3.5 ns typical for VCCB = 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V respectively |
| Propagation Delay B to A at VCCA = 1.2 V | 3.1 ns, 2.7 ns, 2.5 ns, 2.4 ns, 2.3 ns typical for VCCB = 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V respectively |
| Output Enable Time OE to B at VCCA = 1.2 V | 5.1 ns, 4 ns, 3.5 ns, 3.2 ns, 3.1 ns typical for VCCB = 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V respectively |
| Output Disable Time OE to B at VCCA = 1.2 V | 4.7 ns, 4 ns, 4.1 ns, 4.3 ns, 5.1 ns typical for VCCB = 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V respectively |
| A-Port Pins | A1-A8 on pins 3-10, input/output pins referenced to VCCA |
| B-Port Pins | B1-B8 on pins 21, 20, 19, 18, 17, 16, 15, 14, input/output pins referenced to VCCB |
| Supply and Ground Pins | VCCA pin 1; VCCB pins 23 and 24; GND pins 11, 12, and 13 |
| Datasheet Status | request_only |
Product Overview
The SN74AVC8T245 is a Texas Instruments 8-bit noninverting bus transceiver for configurable voltage translation between two supply domains. The A port tracks VCCA and the B port tracks VCCB, with both rails recommended from 1.2 V to 3.6 V. Operation is optimized from 1.4 V to 3.6 V, and the supported translation nodes are 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
DIR and OE are supplied and referenced by VCCA. DIR controls A-to-B or B-to-A data transmission, while OE disables the outputs to isolate the buses; pulling OE high places the outputs in 3-state mode. If either VCC input is at GND, all I/O ports enter high impedance, and Ioff circuitry supports partial-power-down conditions by disabling outputs to reduce damaging current backflow.
The device is available in RHL VQFN-24, PW TSSOP-24, and DGV TVSOP-24 package options. It supports up to 170 Mbps when either supply is below 1.8 V and up to 320 Mbps when both supplies are at least 1.8 V. Recommended free-air operating temperature is -40°C to 125°C.
Key Features
- 8-bit noninverting bus transceiver with configurable voltage translation
- Dual VCCA and VCCB rails from 1.2 V to 3.6 V
- Supports 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V nodes
- DIR and OE control pins are referenced to VCCA
- OE high places outputs in 3-state bus isolation mode
- All I/O ports become high impedance if either VCC is grounded
- Ioff circuitry supports partial-power-down output disabling
- I/Os are tolerant up to 4.6 V
- Maximum data rate reaches 320 Mbps with both rails at least 1.8 V
- Operates across -40°C to 125°C free-air temperature
Typical Applications
- Low-voltage bus voltage translation
- Bidirectional digital interface bridging
- A-port to B-port data transfer
- B-port to A-port data transfer
- 3-state bus isolation
- Partial-power-down interface protection
- Mixed 1.2 V to 3.3 V logic buses
- Asynchronous bus communication
Procurement Notes
When requesting a quote for SN74AVC8T245, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What type of device is the SN74AVC8T245?
The SN74AVC8T245 is an 8-bit noninverting bus transceiver from Texas Instruments. It provides configurable voltage translation between VCCA-referenced A-port signals and VCCB-referenced B-port signals, with 3-state outputs controlled through OE.
What supply voltages does SN74AVC8T245 support?
Both VCCA and VCCB are recommended for 1.2 V to 3.6 V operation. The datasheet describes optimized operation from 1.4 V to 3.6 V and operation with both rails as low as 1.2 V.
How fast can this bus transceiver operate?
The maximum data rate is 170 Mbps when VCCA or VCCB is below 1.8 V. When both VCCA and VCCB are at least 1.8 V, the maximum data rate is specified as 320 Mbps.
How are the DIR and OE control pins referenced?
DIR and OE are supplied and referenced by VCCA. DIR selects A-to-B or B-to-A data transmission, while OE disables the outputs for bus isolation; pulling OE high places the outputs in 3-state mode.
What package options are listed for SN74AVC8T245?
The extracted package options are RHL VQFN-24 at 5.5 mm x 3.5 mm, PW TSSOP-24 at 7.8 mm x 6.4 mm, and DGV TVSOP-24 at 5 mm x 6.4 mm.
What happens if one supply rail is grounded?
The VCC isolation feature places all I/O ports in a high-impedance state if either VCC input is at GND. The part also includes Ioff circuitry for partial-power-down applications.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.