Specifications
| Type | Description |
|---|---|
| Part Number | TPS5450DDAR |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Inferred Category | Power_Management |
| Component Type | Power_IC |
| Package / Case | DDA package, thermally enhanced 8-pin SOIC PowerPAD / HSOP (8), body size 4.89 mm × 3.90 mm |
| Input Voltage Range | 5.5-36 V; recommended operating condition |
| Continuous Output Current | Up to 5 A; device capability |
| Peak Output Current | 6 A; device capability |
| Output Voltage Range | Adjustable down to 1.22 V; feedback reference limited minimum output |
| Initial Output Accuracy | 1.5%; voltage reference / output regulation accuracy |
| Switching Frequency | 400 min, 500 typ, 600 max kHz; internally set free-running frequency |
| Efficiency | >90%; enabled by 110-mΩ integrated MOSFET switch |
| Shutdown Supply Current | 18 typ, 50 max µA; ENA = 0 V |
| Quiescent Current | 3 typ, 4.4 max mA; VSENSE = 2 V, not switching, PH pin open |
| UVLO Start Threshold Voltage | 5.3 typ, 5.5 max V; undervoltage lockout |
| UVLO Hysteresis Voltage | 330 mV; undervoltage lockout |
| Voltage Reference Accuracy at TJ = 25°C | 1.202 min, 1.221 typ, 1.239 max V |
| Voltage Reference Accuracy over IO = 0 A to 5 A | 1.196 min, 1.221 typ, 1.245 max V |
| Minimum Controllable On Time | 150 typ, 200 max ns; oscillator parameter |
| Maximum Duty Cycle | 87% min, 89% typ; oscillator parameter |
| ENA Start Threshold Voltage | 1.3 V; enable pin threshold |
| ENA Stop Threshold Voltage | 0.5 V; below this voltage, device stops switching |
| ENA Hysteresis Voltage | 450 mV; enable pin hysteresis |
| Internal Slow-Start Time | 6.6 min, 8 typ, 10 max ms; 0% to 100% |
| Current Limit | 6.0 min, 7.5 typ, 9.0 max A; overcurrent protection |
| Current Limit Hiccup Time | 13 min, 16 typ, 20 max ms; current limit protection |
| Thermal Shutdown Trip Point | 135 min, 162 typ °C; thermal shutdown |
| Thermal Shutdown Hysteresis | 14°C; thermal shutdown |
| High-Side MOSFET On Resistance at VIN = 5.5 V | 150 mΩ |
| High-Side MOSFET On Resistance | 110 typ, 230 max mΩ; output MOSFET |
| Operating Junction Temperature Range | -40 to 125°C; recommended operating condition |
| Absolute Maximum VIN Voltage | -0.3 to 40 V; over operating free-air temperature unless otherwise noted |
| Absolute Maximum PH Voltage | -0.6 to 40 V; steady-state |
| Absolute Maximum PH Transient Voltage | -1.2 V; transient <10 ns |
| Absolute Maximum ENA Voltage | -0.3 to 7 V; over operating free-air temperature unless otherwise noted |
| Absolute Maximum BOOT-PH Voltage | -0.3 to 10 V; over operating free-air temperature unless otherwise noted |
| Absolute Maximum VSENSE Voltage | -0.3 to 3 V; over operating free-air temperature unless otherwise noted |
| PH Leakage Current | 10 µA; absolute maximum rating |
| Absolute Maximum Operating Virtual Junction Temperature | -40 to 150°C; stress rating |
| Storage Temperature | -65 to 150°C; absolute maximum rating |
| ESD Rating HBM | ±2000 V; human-body model per ANSI/ESDA/JEDEC JS-001 |
| ESD Rating CDM | ±1500 V; charged-device model per JEDEC JESD22-C101 |
| Junction-to-Ambient Thermal Resistance, Custom Board | 30°C/W; DDA 8-pin package |
| Junction-to-Ambient Thermal Resistance, Standard Board | 42.3°C/W; DDA 8-pin package |
| Junction-to-Top Characterization Parameter | 4.9°C/W; DDA 8-pin package |
| Junction-to-Board Characterization Parameter | 20.7°C/W; DDA 8-pin package |
| Junction-to-Case Top Thermal Resistance | 46.4°C/W; DDA 8-pin package |
| Junction-to-Case Bottom Thermal Resistance | 0.8°C/W; DDA 8-pin package |
| Junction-to-Board Thermal Resistance | 20.8°C/W; DDA 8-pin package |
| Control Topology | Constant-frequency voltage-mode control with voltage feedforward; device overview |
| Integrated Switch | High-side N-channel MOSFET; integrated power stage |
| Bootstrap Capacitor Recommendation | 0.01 µF low-ESR capacitor; connect from BOOT pin to PH pin |
| Datasheet Status | request_only |
Product Overview
TPS5450DDAR is a Texas Instruments Power_Management Power_IC configured as a 5-A step-down buck converter. The device operates from a recommended 5.5-36 V input range and regulates an adjustable output down to 1.22 V, with output capability up to 5 A continuous and 6 A peak. Its control architecture is constant-frequency voltage-mode control with voltage feedforward, and the internally set switching frequency is specified at 400 kHz minimum, 500 kHz typical, and 600 kHz maximum.
The power stage integrates a high-side N-channel MOSFET. The MOSFET on-resistance is specified as 150 mΩ at VIN = 5.5 V and 110 mΩ typical, 230 mΩ maximum for the output MOSFET condition. Efficiency is stated as greater than 90%, enabled by the 110-mΩ integrated MOSFET switch. Protection and sequencing functions include UVLO, ENA thresholds, 6.6-10 ms internal slow start, current-limit hiccup timing, and thermal shutdown.
The DDA package is a thermally enhanced 8-pin SOIC PowerPAD / HSOP (8) with a 4.89 mm × 3.90 mm body. Thermal data includes 30°C/W junction-to-ambient on a custom board and 42.3°C/W on a standard board. A 0.01 µF low-ESR bootstrap capacitor is recommended from BOOT to PH.
Key Features
- 5.5-36 V recommended input operating range
- Up to 5 A continuous output current
- 6 A peak output current capability
- Adjustable output voltage down to 1.22 V
- 400-600 kHz internally set switching frequency
- Greater than 90% efficiency with integrated MOSFET
- Constant-frequency voltage-mode control with voltage feedforward
- Integrated high-side N-channel MOSFET switch
- Internal 6.6-10 ms slow-start timing
- Current-limit hiccup and thermal shutdown protection
Typical Applications
- 5.5-36 V step-down rails
- 5-A point-of-load conversion
- Adjustable 1.22 V supplies
- Enable-controlled power sequencing
- Thermally enhanced PowerPAD assemblies
- High-frequency buck converter layouts
Procurement Notes
When requesting a quote for TPS5450DDAR, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What input voltage range does TPS5450DDAR support?
TPS5450DDAR has a recommended operating input voltage range of 5.5-36 V. Absolute maximum VIN is specified separately as -0.3 to 40 V and should be treated as a stress rating, not the normal operating range.
How much output current can TPS5450DDAR deliver?
The device capability is up to 5 A continuous output current and 6 A peak output current. Current-limit protection is specified at 6.0 A minimum, 7.5 A typical, and 9.0 A maximum.
What package is used for TPS5450DDAR?
TPS5450DDAR uses the DDA package, described as a thermally enhanced 8-pin SOIC PowerPAD / HSOP (8). The package body size is 4.89 mm × 3.90 mm.
What bootstrap capacitor is recommended for TPS5450DDAR?
The datasheet facts specify a 0.01 µF low-ESR capacitor connected from the BOOT pin to the PH pin as the bootstrap capacitor recommendation for this converter.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.