Specifications
| Type | Description |
|---|---|
| Part Number | AM62A7 |
| Manufacturer | Texas Instruments |
| Product Type | Sitara application processor SoC |
| Category | Microcontroller |
| Package / Case | AMB FCBGA 484-pin, 18 mm x 18 mm, 0.8 mm pitch; ANF FCCSP 484-pin, 18 mm x 18 mm, 0.8 mm pitch |
| CPU subsystem | Up to quad 64-bit Arm Cortex-A53; microprocessor subsystem, up to 1.4 GHz |
| Cortex-A53 L2 cache | 512 KB shared L2 cache with SECDED ECC; quad-core Cortex-A53 cluster |
| Cortex-A53 L1 data cache | 32 KB per core with SECDED ECC; each A53 core |
| Cortex-A53 L1 instruction cache | 32 KB per core with parity protection; each A53 core |
| MCU core | Single-core Arm Cortex-R5F up to 800 MHz; integrated as part of MCU channel with FFI |
| MCU R5F memory | 32 KB ICache, 32 KB L1 DCache, 64 KB TCM with SECDED ECC; MCU channel Cortex-R5F |
| Device management core | Single-core Arm Cortex-R5F up to 800 MHz; device management support |
| Deep learning accelerator DSP | Single-core C7x floating-point 256-bit vector DSP, up to 40 GFLOPS at 1.0 GHz |
| Matrix multiply accelerator | Up to 2 TOPS, 8-bit, at 1.0 GHz; MMA in Deep Learning Accelerator |
| C7x cache and SRAM | 64 KB L1 DCache with SECDED ECC, 32 KB L1 ICache with parity, 1.25 MB L2 SRAM with SECDED ECC |
| Vision ISP throughput | 315 MPixel/s; up to 5 MP at 60 fps; VPAC Image Signal Processor |
| Vision input format | Up to 16-bit input RAW; supports 12-bit RGB-IR; VPAC ISP |
| Camera interface | One CSI-2 receiver with 4-lane D-PHY; MIPI CSI-2 v1.3 compliant, MIPI D-PHY 1.2 |
| CSI-2 lane rate | Up to 2.5 Gbps per lane; 1, 2, 3, or 4 data lane mode |
| Video codec support | HEVC H.265 Main profile Level 5.1 High-tier; H.264 Baseline/Main/High profiles Level 5.2 |
| Video resolution | Up to 4K UHD, 3840 x 2160; video encoder/decoder |
| JPEG encode rate | 416 MPixels/s, resolutions up to 4K UHD 3840 x 2160; Motion JPEG encode |
| Display support | Single display up to 2048 x 1080 at 60 fps; display subsystem |
| Display pixel clock | Up to 165 MHz; independent PLL, DPI 24-bit RGB parallel interface |
| On-chip RAM total | Up to 2.29 MB; memory subsystem |
| DDR support | LPDDR4, 32-bit data bus with inline ECC, up to 3733 MT/s; DDR subsystem |
| DDR addressable range | Maximum 8 GB; DDR subsystem |
| Ethernet | Integrated Ethernet switch with total 2 external ports; RMII 10/100 or RGMII 10/100/1000 |
| USB ports | 2x USB 2.0 ports; configurable as host, peripheral, or dual-role device with VBUS detection |
| UART interfaces | 9x UART; general connectivity |
| SPI controllers | 5x SPI controllers; general connectivity |
| I2C ports | 6x I2C ports; general connectivity |
| CAN interfaces | 3x CAN modules with CAN-FD support, up to 8 Mbps; supports CAN Protocol 2.0 A/B and ISO 11898-1 |
| MMC/SD interfaces | 3x MMC/SD/SDIO interfaces: 1x 8-bit eMMC up to HS200, 2x 4-bit SD/SDIO up to UHS-I |
| OSPI/QSPI | DDR/SDR support, Serial NAND and Serial NOR, 4 GB memory address support, XIP with optional on-the-fly encryption |
| Boot options | UART, I2C EEPROM, OSPI/QSPI flash, GPMC NOR/NAND, Serial NAND, SD card, eMMC, USB host, USB device DFU, Ethernet |
| Process technology | 16-nm FinFET |
| Datasheet Status | request_only |
Product Overview
The AM62A7 is a Texas Instruments Sitara application processor SoC categorized here as a Microcontroller. Its processing structure includes up to quad 64-bit Arm Cortex-A53 cores at up to 1.4 GHz, a single-core Arm Cortex-R5F MCU channel up to 800 MHz, and a separate single-core Arm Cortex-R5F device-management core up to 800 MHz.
For vision and AI workloads, the device includes a C7x floating-point 256-bit vector DSP rated up to 40 GFLOPS at 1.0 GHz and a matrix multiply accelerator rated up to 2 TOPS for 8-bit operation at 1.0 GHz. The VPAC ISP supports 315 MPixel/s throughput and up to 5 MP at 60 fps, with up to 16-bit RAW input and 12-bit RGB-IR support.
Memory and interfaces include up to 2.29 MB on-chip RAM, LPDDR4 with a 32-bit data bus and inline ECC up to 3733 MT/s, and a maximum 8 GB DDR addressable range. Package options are AMB FCBGA and ANF FCCSP, both 484-pin, 18 mm x 18 mm, 0.8 mm pitch, manufactured on 16-nm FinFET technology.
Key Features
- Quad 64-bit Arm Cortex-A53 subsystem up to 1.4 GHz
- Cortex-R5F MCU channel operates up to 800 MHz
- C7x vector DSP delivers up to 40 GFLOPS
- Matrix multiply accelerator supports up to 2 TOPS
- VPAC ISP supports 315 MPixel/s image throughput
- CSI-2 receiver supports four-lane D-PHY operation
- Video codec supports H.265 and H.264 profiles
- LPDDR4 interface supports inline ECC and 3733 MT/s
- Integrated Ethernet switch provides two external ports
- Three CAN modules support CAN-FD up to 8 Mbps
- OSPI/QSPI supports Serial NAND, NOR, and XIP
- Manufactured using 16-nm FinFET process technology
Typical Applications
- Embedded vision processing
- Edge AI inference
- Camera-based inspection systems
- 4K video encode and decode
- Networked industrial controllers
- CAN-FD connected equipment
- Display-enabled embedded systems
- LPDDR4-based application processing
Procurement Notes
When requesting a quote for AM62A7, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What processor cores are integrated in the AM62A7?
The AM62A7 includes up to a quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4 GHz, a single-core Arm Cortex-R5F MCU channel up to 800 MHz, and a single-core Arm Cortex-R5F device-management core.
What AI acceleration resources does the AM62A7 provide?
The device includes a single-core C7x floating-point 256-bit vector DSP rated up to 40 GFLOPS at 1.0 GHz, plus a matrix multiply accelerator rated up to 2 TOPS for 8-bit operation at 1.0 GHz.
What camera and vision interfaces are supported by AM62A7?
AM62A7 provides one MIPI CSI-2 v1.3 receiver with a 4-lane D-PHY and lane rates up to 2.5 Gbps per lane. The VPAC ISP supports 315 MPixel/s throughput, up to 5 MP at 60 fps, 16-bit RAW input, and 12-bit RGB-IR.
What memory interfaces are specified for the AM62A7?
The AM62A7 supports up to 2.29 MB of on-chip RAM and an LPDDR4 DDR subsystem with a 32-bit data bus, inline ECC, and data rates up to 3733 MT/s. The maximum DDR addressable range is 8 GB.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.