Specifications
| Type | Description |
|---|---|
| Part Number | AM3352 |
| Manufacturer | Texas Instruments |
| Product Type | Sitara ARM Cortex-A8 processor |
| Category | Microcontroller |
| Component Type | MCU |
| Package / Case | AM3352ZCZ: NFBGA-324, 15.0 mm x 15.0 mm; AM3352ZCE: NFBGA-298, 13.0 mm x 13.0 mm |
| CPU Core | ARM Cortex-A8 32-bit RISC processor |
| Maximum CPU Frequency | up to 1 GHz |
| L1 Cache | 32 KB instruction cache and 32 KB data cache, with single-error detection parity |
| L2 Cache | 256 KB, with ECC |
| Boot ROM | 176 KB on-chip boot ROM |
| Dedicated RAM | 64 KB on-chip dedicated RAM |
| Shared L3 RAM | 64 KB general-purpose OCMC RAM, accessible to all masters |
| External Memory Interface | mDDR, DDR2, DDR3, DDR3L |
| mDDR Data Rate | 400 MHz, 200 MHz clock |
| DDR2 Data Rate | 532 MHz, 266 MHz clock |
| DDR3 Data Rate | 800 MHz, 400 MHz clock |
| DDR3L Data Rate | 800 MHz, 400 MHz clock |
| External Memory Data Bus Width | 16-bit EMIF memory interface |
| Total Addressable External Memory Space | 1 GB through EMIF |
| GPMC Interface Width | 8-bit and 16-bit asynchronous memory interface for NAND, NOR, muxed-NOR, SRAM |
| GPMC Chip Selects | up to 7 |
| NAND ECC Support | 1-bit Hamming; 4-, 8-, or 16-bit BCH ECC with ELM error locator module |
| PRU Count | 2 programmable real-time units in PRU-ICSS subsystem |
| PRU Frequency | 200 MHz, 32-bit load/store RISC processor |
| PRU Instruction RAM | 8 KB per PRU, with single-error detection parity |
| PRU Data RAM | 8 KB per PRU, with single-error detection parity |
| PRU Shared RAM | 12 KB, with single-error detection parity |
| USB Ports | up to 2 USB 2.0 High-Speed dual-role-device ports with integrated PHY |
| Ethernet MACs | up to 2 industrial gigabit Ethernet MACs, 10/100/1000 Mbps, integrated switch |
| Ethernet Interfaces | MII, RMII, RGMII, MDIO for each Ethernet MAC |
| CAN Ports | up to 2, supports CAN Version 2 Parts A and B |
| UART Interfaces | up to 6, IrDA and CIR modes supported; RTS/CTS flow control supported |
| SPI Interfaces | up to 2 McSPI master/slave interfaces, up to 2 chip selects, up to 48 MHz |
| MMC SD SDIO Ports | up to 3, 1-bit, 4-bit, and 8-bit modes; up to 48 MHz data transfer rate |
| I2C Interfaces | up to 3 master/slave interfaces, standard mode up to 100 kHz, fast mode up to 400 kHz |
| GPIO | up to 4 banks, 32 GPIO pins per bank, multiplexed with other functional pins |
| General-Purpose Timers | 8 x 32-bit timers; DMTIMER1 is a 1-ms OS tick timer; DMTIMER4-DMTIMER7 pinned out |
| Watchdog Timer | 1 on-chip watchdog timer |
| ADC | 12-bit SAR ADC, 200 kSamples/s, input selectable from 8 analog inputs through 8:1 analog switch |
| Touchscreen Controller | 4-wire, 5-wire, or 8-wire resistive touchscreen interface via configurable ADC |
| PWM Modules | up to 3 enhanced high-resolution PWM modules; configurable as 6 single-ended, 6 dual-edge symmetric, or 3 dual-edge asymmetric outputs |
| eCAP Modules | up to 3 32-bit eCAP modules, configurable as 3 capture inputs or 3 auxiliary PWM outputs |
| eQEP Modules | up to 3 32-bit enhanced quadrature encoder pulse modules |
| DMA Controller | EDMA with 3 TPTCs and 1 TPCC; supports up to 64 programmable logical channels and 8 QDMA channels |
| RTC Oscillator | 32.768 kHz internal RTC oscillator with RTC logic and 1.1 V internal LDO |
| High-Frequency Oscillator | 15 MHz to 35 MHz integrated oscillator used to generate reference clocks |
| Datasheet Status | request_only |
Product Overview
The AM3352 is a Texas Instruments Sitara ARM Cortex-A8 processor categorized here as a Microcontroller. Its CPU subsystem uses an ARM Cortex-A8 32-bit RISC processor operating up to 1 GHz, with 32 KB instruction cache, 32 KB data cache, and 256 KB L2 cache with ECC. On-chip memory resources include 176 KB boot ROM, 64 KB dedicated RAM, and 64 KB shared L3 OCMC RAM accessible to all masters.
External memory is handled through an EMIF supporting mDDR, DDR2, DDR3, and DDR3L with a 16-bit data bus and 1 GB total addressable external memory space. The GPMC supports 8-bit and 16-bit asynchronous interfaces for NAND, NOR, muxed-NOR, and SRAM, with up to 7 chip selects and NAND ECC options including Hamming and BCH modes.
For embedded control and connectivity designs, AM3352 integrates PRU-ICSS with two 200 MHz programmable real-time units, USB 2.0 dual-role ports, industrial gigabit Ethernet MACs, CAN, UART, SPI, MMC/SD/SDIO, I2C, GPIO, timers, watchdog, ADC, resistive touchscreen support, PWM, eCAP, eQEP, EDMA, RTC, and clock oscillator functions. Package options are NFBGA-324 and NFBGA-298.
Key Features
- ARM Cortex-A8 32-bit RISC processor up to 1 GHz
- 32 KB instruction and 32 KB data L1 caches
- 256 KB L2 cache with ECC protection
- mDDR, DDR2, DDR3, and DDR3L EMIF support
- 16-bit external memory bus with 1 GB address space
- Two 200 MHz PRUs in the PRU-ICSS subsystem
- Up to two USB 2.0 High-Speed dual-role ports
- Up to two industrial gigabit Ethernet MACs
- Up to six UART interfaces with RTS/CTS flow control
- 12-bit SAR ADC with 200 kSamples/s rate
- Up to three enhanced high-resolution PWM modules
- EDMA supports 64 logical channels and 8 QDMA channels
Typical Applications
- Industrial Ethernet controllers
- CAN network nodes
- Resistive touchscreen interfaces
- PWM-based control outputs
- Quadrature encoder interfaces
- USB dual-role embedded devices
- External DDR memory systems
- NAND, NOR, SRAM memory interfaces
- ADC-based analog input systems
Procurement Notes
When requesting a quote for AM3352, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What processor core is integrated in the AM3352?
The AM3352 integrates an ARM Cortex-A8 32-bit RISC processor. The extracted datasheet facts specify operation up to 1 GHz for the Sitara ARM Cortex-A8 processor.
Which external memory types does AM3352 support?
The AM3352 EMIF memory controller supports mDDR, DDR2, DDR3, and DDR3L. The extracted facts also specify a 16-bit external memory data bus and 1 GB total addressable external memory space.
What package options are listed for AM3352?
The provided package information lists AM3352ZCZ as NFBGA-324 measuring 15.0 mm x 15.0 mm and AM3352ZCE as NFBGA-298 measuring 13.0 mm x 13.0 mm.
What real-time processing resources does the AM3352 include?
AM3352 includes the PRU-ICSS subsystem with two programmable real-time units. Each PRU is specified as a 200 MHz 32-bit load/store RISC processor with 8 KB instruction RAM and 8 KB data RAM.
What connectivity interfaces are available on AM3352?
The extracted facts list up to two USB 2.0 High-Speed dual-role ports, up to two industrial gigabit Ethernet MACs, up to two CAN ports, up to six UARTs, up to two SPI interfaces, up to three MMC/SD/SDIO ports, and up to three I2C interfaces.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.