Specifications
| Type | Description |
|---|---|
| Part Number | SN74LVC2T45DCUR |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package Case | DCU (VSSOP, 8), 2 mm × 3.1 mm |
| Function | Dual-bit noninverting dual-supply bus transceiver with configurable voltage translation |
| A-Port Supply Voltage Range | 1.65 V to 5.5 V |
| B-Port Supply Voltage Range | 1.65 V to 5.5 V |
| Supported Voltage Translation Nodes | 1.8 V, 2.5 V, 3.3 V, 5 V |
| Number of Channels | 2 bits |
| Direction Control Reference | DIR input referenced to VCCA |
| Direction Mode | A bus to B bus |
| Direction Mode | B bus to A bus |
| VCC Isolation | Both ports high-impedance if either VCC input is at GND |
| Partial-Power-Down Support | Ioff circuitry disables outputs to prevent damaging current backflow when powered down |
| Maximum ICC | 4 µA max |
| Total Supply Current | 4 µA max, ICCA + ICCB, VI = VCCI or GND, IO = 0, VCCA/VCCB = 1.65 V to 5.5 V |
| Output Drive Current | ±24 mA at 3.3 V |
| High-Level Output Current | -24 mA, VCCO = 3 V to 3.6 V |
| Low-Level Output Current | 24 mA, VCCO = 3 V to 3.6 V |
| High-Level Output Current | -32 mA, VCCO = 4.5 V to 5.5 V |
| Low-Level Output Current | 32 mA, VCCO = 4.5 V to 5.5 V |
| Maximum Data Rate | 420 Mbps, 3.3 V to 5 V translation |
| Maximum Data Rate | 210 Mbps, translate to 3.3 V |
| Maximum Data Rate | 140 Mbps, translate to 2.5 V |
| Maximum Data Rate | 75 Mbps, translate to 1.8 V |
| Operating Free-Air Temperature | -40 °C to 85 °C |
| Absolute Maximum Supply Voltage | -0.5 V to 6.5 V, VCCA or VCCB |
| Absolute Maximum Input Voltage | -0.5 V to 6.5 V |
| Absolute Maximum High-Impedance Output Voltage | -0.5 V to 6.5 V |
| Continuous Output Current | -50 mA to 50 mA |
| Continuous Current Through VCC or GND | -100 mA to 100 mA |
| Junction Temperature | 150 °C max |
| Storage Temperature | -65 °C to 150 °C |
| ESD Rating HBM | ±4000 V |
| ESD Rating CDM | ±1000 V |
| Latch-Up Performance | Exceeds 100 mA per JESD 78, Class II |
| Input Voltage Range | 0 V to 5.5 V |
| Output Voltage Range | 0 V to VCCO |
| Data Input VIH | VCCI × 0.65 min, VCCI = 1.65 V to 1.95 V |
| Data Input VIL | VCCI × 0.35 max, VCCI = 1.65 V to 1.95 V |
| Data Input VIH | 1.7 V min, VCCI = 2.3 V to 2.7 V |
| Data Input VIL | 0.7 V max, VCCI = 2.3 V to 2.7 V |
| Data Input VIH | 2 V min, VCCI = 3 V to 3.6 V |
| Data Input VIL | 0.8 V max, VCCI = 3 V to 3.6 V |
| Data Input VIH | VCCI × 0.7 min, VCCI = 4.5 V to 5.5 V |
| Data Input VIL | VCCI × 0.3 max, VCCI = 4.5 V to 5.5 V |
| DIR Input VIH | VCCA × 0.65 min, VCCA = 1.65 V to 1.95 V |
| DIR Input VIL | VCCA × 0.35 max, VCCA = 1.65 V to 1.95 V |
| DIR Input VIH | 1.7 V min, VCCA = 2.3 V to 2.7 V |
| DIR Input VIL | 0.7 V max, VCCA = 2.3 V to 2.7 V |
| DIR Input VIH | 2 V min, VCCA = 3 V to 3.6 V |
| DIR Input VIL | 0.8 V max, VCCA = 3 V to 3.6 V |
| DIR Input VIH | VCCA × 0.7 min, VCCA = 4.5 V to 5.5 V |
| DIR Input VIL | VCCA × 0.3 max, VCCA = 4.5 V to 5.5 V |
| Input Transition Rise/Fall Rate | 20 ns/V max, data inputs, VCCI = 1.65 V to 2.7 V |
| Input Transition Rise/Fall Rate | 10 ns/V max, data inputs, VCCI = 3 V to 3.6 V |
| Input Transition Rise/Fall Rate | 5 ns/V max, data inputs VCCI = 4.5 V to 5.5 V; control input VCCA = 1.65 V to 5.5 V |
| VOH | VCCO - 0.1 V min, IOH = -100 µA, VCCA/VCCB = 1.65 V to 4.5 V |
| VOL | 0.1 V max, IOL = 100 µA, VCCA/VCCB = 1.65 V to 4.5 V |
| DIR Input Leakage Current | ±2 µA max |
| Power-Off Leakage Current | ±2 µA max, A port, VCCA = 0 V, VCCB = 0 V to 5.5 V |
| Power-Off Leakage Current | ±2 µA max, B port, VCCA = 0 V to 5.5 V, VCCB = 0 V |
| High-Impedance Output Leakage | ±2 µA max |
| DIR Input Capacitance | 2.5 pF typ |
| A/B Port I/O Capacitance | 6 pF typ |
| Propagation Delay A to B | 1.7 ns to 8.3 ns, tPLH, VCCA = 1.8 V ±0.15 V, VCCB = 3.3 V ±0.3 V |
| Propagation Delay A to B | 1.8 ns to 7.1 ns, tPHL, VCCA = 1.8 V ±0.15 V, VCCB = 3.3 V ±0.3 V |
| Propagation Delay A to B | 1.1 ns to 5.1 ns, tPLH, VCCA = 2.5 V ±0.2 V, VCCB = 5 V ±0.5 V |
| Propagation Delay A to B | 0.9 ns to 4.6 ns, tPHL, VCCA = 2.5 V ±0.2 V, VCCB = 5 V ±0.5 V |
| Thermal Resistance Junction-to-Ambient | 246.4 °C/W, DCU package, 8 pins |
| Thermal Resistance Junction-to-Case Top | 95.4 °C/W, DCU package, 8 pins |
| Thermal Resistance Junction-to-Board | 157.8 °C/W, DCU package, 8 pins |
| Pin 1 | VCCA, A-port supply voltage |
| Pin 2 | A1, input/output A1 referenced to VCCA |
| Pin 3 | A2, input/output A2 referenced to VCCA |
| Pin 4 | GND, ground |
| Pin 5 | DIR, direction control signal |
| Pin 6 | B2, input/output B2 referenced to VCCB |
| Pin 7 | B1, input/output B1 referenced to VCCB |
| Pin 8 | VCCB, B-port supply voltage |
| Datasheet Status | request_only |
Product Overview
Direction is controlled by the DIR input, which is referenced to VCCA. Depending on the DIR logic level, the device activates either A-bus-to-B-bus or B-bus-to-A-bus transfer. If either VCC input is at GND, both ports enter a high-impedance state. Ioff circuitry disables outputs during partial-power-down conditions to help prevent damaging current backflow.
Key Features
- Dual-bit noninverting dual-supply bus transceiver
- Configurable bidirectional voltage translation between A and B buses
- VCCA and VCCB supply ranges: 1.65 V to 5.5 V
- Supports 1.8 V, 2.5 V, 3.3 V, and 5 V nodes
- DIR input referenced to VCCA for direction control
- Both ports high-impedance when either VCC input is grounded
- Ioff circuitry disables outputs during partial-power-down conditions
- 4 µA maximum total supply current
- 420 Mbps maximum for 3.3 V to 5 V translation
- DCU VSSOP 8-pin package, 2 mm × 3.1 mm
Typical Applications
- 1.8 V to 3.3 V bus translation
- 3.3 V to 5 V bus translation
- Dual-bit bidirectional signal interfaces
- Mixed-voltage signal-chain buses
- Partial-power-down bus isolation
- Low-current voltage translation nodes
Procurement Notes
When requesting a quote for SN74LVC2T45DCUR, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is SN74LVC2T45DCUR?
SN74LVC2T45DCUR is a dual-bit noninverting dual-supply bus transceiver with configurable voltage translation. It provides A1/A2 and B1/B2 bus channels for bidirectional translation between A and B voltage domains.
What supply voltage ranges does the device support?
The A-port supply VCCA and B-port supply VCCB are each specified from 1.65 V to 5.5 V. The device supports translation nodes at 1.8 V, 2.5 V, 3.3 V, and 5 V.
How is direction control handled on SN74LVC2T45DCUR?
Direction is controlled by the DIR input, and the DIR input circuit is referenced to VCCA. Depending on the DIR logic level, either the A-bus-to-B-bus path or B-bus-to-A-bus path is activated.
What happens if either supply is at ground?
If either VCC input is at GND, both ports are placed in a high-impedance state. The device also includes Ioff circuitry that disables outputs during powered-down conditions to prevent damaging current backflow.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.