Specifications
| Type | Description |
|---|---|
| Part Number | TPS51604_DDR5-PMIC |
| Manufacturer | Texas Instruments |
| Product Type | Gate Driver IC |
| Category | Power Management |
| Component Type | Power_IC |
| Package Case | 8-pin WSON (DSG), 2.00 mm x 2.00 mm |
| Package Body Size | 2.00 mm x 2.00 mm nominal; TPS51604 WSON(8) package |
| Conversion Input Voltage Range | 4.5 to 28 V; VIN range from features |
| Operating Temperature Range | -40 to 105 °C; device operation |
| VDD Supply Input | 5 V nominal; decouple VDD to GND with ceramic capacitor >=1 µF |
| VDD Absolute Maximum Input Voltage | -0.3 to 6 V; over operating free-air temperature |
| PWM/SKIP Absolute Maximum Input Voltage | -0.3 to 6 V; over operating free-air temperature |
| BST Absolute Maximum Input Voltage | -0.3 to 35 V; over operating free-air temperature |
| BST Transient Absolute Maximum Input Voltage | -0.3 to 38 V; transient <20 ns |
| BST-to-SW and DRVH-to-SW Absolute Maximum Voltage | -0.3 to 6 V; output voltage rating |
| SW Absolute Maximum Voltage | -2 to 30 V; output voltage rating |
| DRVH/SW Transient Absolute Maximum Voltage | -5 to 38 V; transient <20 ns |
| DRVL Absolute Maximum Voltage | -0.3 to 6 V; output voltage rating |
| GND-to-PAD Absolute Maximum Voltage | -0.3 to 0.3 V; ground pins |
| Operating Junction Temperature Absolute Maximum | -40 to 125 °C; absolute maximum ratings |
| Storage Temperature Range | -55 to 150 °C; absolute maximum ratings |
| ESD Rating HBM | ±2000 V; human body model, per AEC Q100-002 |
| ESD Rating CDM | ±750 V; charged device model, per AEC Q100-011 |
| Recommended VDD Input Voltage | 4.5 V min, 5 V nom, 5.5 V max; recommended operating conditions |
| Recommended PWM/SKIP Input Voltage | -0.1 to 5.5 V; recommended operating conditions |
| Recommended BST Input Voltage | -0.1 to 34 V; recommended operating conditions |
| Recommended BST-to-SW and DRVH-to-SW Voltage | -0.1 to 5.5 V; recommended operating conditions |
| Recommended SW Voltage | -1 to 28 V; recommended operating conditions |
| Recommended DRVL Voltage | -0.1 to 5.5 V; recommended operating conditions |
| Recommended GND-to-PAD Voltage | -0.1 to 0.1 V; recommended operating conditions |
| Recommended Operating Junction Temperature | -40 to 105 °C; recommended operating conditions |
| Junction-to-Ambient Thermal Resistance | 63.1 °C/W; WSON(DSG), 8 pins |
| Junction-to-Case Top Thermal Resistance | 74.1 °C/W; WSON(DSG), 8 pins |
| Junction-to-Board Thermal Resistance | 34.3 °C/W; WSON(DSG), 8 pins |
| Junction-to-Top Characterization Parameter | 2.0 °C/W; WSON(DSG), 8 pins |
| Junction-to-Board Characterization Parameter | 34.9 °C/W; WSON(DSG), 8 pins |
| Junction-to-Case Bottom Thermal Resistance | 11.7 °C/W; WSON(DSG), 8 pins |
| Operating Supply Current, PWM High | 160 µA typ, 600 µA max; VSKIP=VDD or VSKIP=0 V, PWM=High, VDD=5 V, -40°C<=TJ<=105°C |
| Operating Supply Current, PWM Low | 250 µA typ; VSKIP=VDD or VSKIP=0 V, PWM=Low, VDD=5 V, -40°C<=TJ<=105°C |
| Low-Power Supply Current | 130 µA typ; VSKIP=VDD or VSKIP=0 V, PWM=Float, VDD=5 V, -40°C<=TJ<=105°C |
| Very-Low-Power Supply Current | 8 µA typ; VSKIP=Float, VDD=5 V, -40°C<=TJ<=105°C |
| UVLO Rising Threshold | 4.15 V typ; VDD undervoltage lockout |
| UVLO Falling Threshold | 3.7 V typ; VDD undervoltage lockout |
| UVLO Hysteresis | 0.2 V typ; VDD undervoltage lockout |
| PWM/SKIP Pullup Input Impedance | 1.7 MΩ typ; pullup to VDD |
| PWM/SKIP Pulldown Input Impedance | 800 kΩ typ; pulldown to GND |
| Low-Level Input Voltage | 0.6 V max; PWM and SKIP I/O specifications |
| High-Level Input Voltage | 2.65 V min; PWM and SKIP I/O specifications |
| Input Hysteresis | 0.2 V typ; PWM and SKIP I/O specifications |
| Tri-State Voltage | 1.3 V min, 2.0 V max; PWM and SKIP I/O specifications |
| PWM Falling Tri-State Activation Time | 60 ns typ; tTHOLD(off1), PWM |
| PWM Rising Tri-State Activation Time | 60 ns typ; tTHOLD(off2), PWM |
| SKIP Falling Tri-State Activation Time | 1 µs typ; tTSKF, SKIP |
| SKIP Rising Tri-State Activation Time | 1 µs typ; tTSKR, SKIP |
| PWM Tri-State Exit Time | 100 ns typ; t3RD(PWM) |
| SKIP Tri-State Exit Time | 50 µs typ; t3RD(SKIP) |
| DRVH Rise Time | 30 ns typ; CDRVH=3.3 nF, 20% to 80% |
| DRVH Rise-Time Propagation Delay | 40 ns typ; CDRVH=3.3 nF |
| DRVH Source Resistance | 4 Ω typ, 8 Ω max; (VBST-VSW)=5 V, high state, (VBST-VDRVH)=0.1 V |
| DRVH Fall Time | 8 ns typ; DRVH falling, CDRVH=3.3 nF |
| DRVH Fall-Time Propagation Delay | 25 ns typ; CDRVH=3.3 nF |
| DRVH Sink Resistance | 0.5 Ω typ, 1.6 Ω max; (VBST-VSW) forced to 5 V, low state, (VDRVH-VSW)=0.1 V |
| DRVH-to-SW Resistance | 100 kΩ typ; specified by design, not production tested |
| DRVL Rise Time | 15 ns typ; DRVL rising, CDRVL=3.3 nF, 20% to 80% |
| DRVL Rise-Time Propagation Delay | 35 ns typ; CDRVL=3.3 nF |
| DRVL Source Resistance | 1.5 Ω typ, 3 Ω max; (VVDD-GND)=5 V, high state, (VVDD-VDRVL)=0.1 V |
| DRVL Fall Time | 10 ns typ; DRVL falling, CDRVL=3.3 nF |
| DRVL Fall-Time Propagation Delay | 15 ns typ; CDRVL=3.3 nF |
| DRVL Sink Resistance | 0.4 Ω typ, 1.6 Ω max; (VVDD-GND)=5 V, low state, (VDRVL-GND)=0.1 V |
| DRVL-to-GND Resistance | 100 kΩ typ; specified by design, not production tested |
| Gate Driver Dead-Time Rising Edge | 0 ns min, 20 ns typ, 35 ns max; tR(DT) |
| Gate Driver Dead-Time Falling Edge | 0 ns min, 10 ns typ, 25 ns max; tF(DT) |
| Zero-Crossing Comparator Offset | -2.25 mV min, 0 mV typ, 2.00 mV max; SW voltage rising |
| Bootstrap Switch Forward Voltage | 120 mV typ, 240 mV max; IF=10 mA |
| Bootstrap Switch Reverse Leakage | 2 µA max; (VBST-VVDD)=25 V |
| Bootstrap Switch On-Resistance | 12 Ω typ, 24 Ω max; integrated bootstrap switch |
| PWM Tri-State Function | Turns off both DRVH and DRVL; tri-state voltage applied to PWM pin |
| SKIP Low Function | Zero-crossing comparator active; enters discontinuous conduction mode when inductor current reaches zero; SKIP=LO |
| SKIP High Function | Zero-crossing comparator disabled; driver outputs follow PWM input; SKIP=HI |
| SKIP Tri-State Function | Driver enters very-low-power state; tri-state voltage applied to SKIP pin |
| Datasheet Status | request_only |
Product Overview
TPS51604_DDR5-PMIC is a Texas Instruments synchronous buck FET driver in the Power Management category. The device is provided in an 8-pin WSON (DSG) package with a 2.00 mm x 2.00 mm nominal body size, supporting compact synchronous buck power-stage layouts.
The conversion input voltage range is 4.5 to 28 V, while VDD is a 5 V nominal supply input. Recommended VDD operation is 4.5 V minimum, 5 V nominal, and 5.5 V maximum, with device operation specified across -40 to 105 °C. The datasheet also specifies absolute maximum ratings for VDD, PWM/SKIP, BST, SW, DRVH, DRVL, GND-to-PAD, operating junction temperature, and storage temperature.
Control behavior is defined through PWM and SKIP pins. A PWM tri-state voltage turns off both DRVH and DRVL. SKIP low enables the zero-crossing comparator and discontinuous conduction mode when inductor current reaches zero, SKIP high disables the zero-crossing comparator, and SKIP tri-state places the driver in a very-low-power state.
Key Features
- 4.5 to 28 V conversion input voltage range
- 5 V nominal VDD supply input
- Recommended VDD range from 4.5 V to 5.5 V
- -40 to 105 °C recommended operating junction temperature
- PWM tri-state turns off both DRVH and DRVL
- SKIP low enables zero-crossing discontinuous conduction mode
- SKIP high disables zero-crossing comparator operation
- SKIP tri-state enters very-low-power state
- DRVH and DRVL outputs support 3.3 nF gate loads
- Integrated bootstrap switch with 12 Ω typical on-resistance
Typical Applications
- Synchronous buck power stages
- DDR5 PMIC power control
- PWM-controlled FET drive
- Discontinuous conduction mode operation
- Zero-crossing comparator buck control
- Compact WSON power-management layouts
- 5 V driver-supply systems
Procurement Notes
When requesting a quote for TPS51604_DDR5-PMIC, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What type of device is TPS51604_DDR5-PMIC?
TPS51604_DDR5-PMIC is a Texas Instruments synchronous buck FET driver in the Power Management category. It is a gate driver IC designed for PWM-controlled synchronous buck power stages.
What package is used for TPS51604_DDR5-PMIC?
The device is supplied in an 8-pin WSON (DSG) package with a 2.00 mm x 2.00 mm body. The datasheet specifies junction-to-ambient thermal resistance of 63.1 °C/W and junction-to-case bottom of 11.7 °C/W.
What is the conversion input voltage range of TPS51604?
The conversion input voltage operating range is specified as 4.5 to 28 V. The recommended VDD input voltage is 4.5 V minimum, 5 V nominal, and 5.5 V maximum.
How do the PWM and SKIP pins control operation?
A PWM tri-state voltage turns off both DRVH and DRVL outputs. SKIP low activates the zero-crossing comparator for discontinuous conduction mode entry, SKIP high disables the comparator, and SKIP tri-state enters a very-low-power state.
What ESD protection does TPS51604_DDR5-PMIC offer?
The device provides ±2000 V HBM (human body model) and ±750 V CDM (charged device model) ESD ratings as specified in the datasheet absolute maximum ratings.
Can I source TPS51604_DDR5-PMIC through LDeepAI?
LDeepAI provides sourcing support for Texas Instruments parts including TPS51604_DDR5-PMIC. Submit an RFQ for current pricing, lead time and availability information.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.