Specifications
| Type | Description |
|---|---|
| Part Number | AM62A7 |
| Manufacturer | Texas Instruments |
| Product Type | Sitara AI vision processor |
| Category | Microcontroller |
| Package / Case | AMB FCBGA 484-pin, 18 mm x 18 mm, 0.8 mm pitch; ANF FCCSP 484-pin, 18 mm x 18 mm, 0.8 mm pitch |
| Application CPU | Up to quad 64-bit Arm Cortex-A53; microprocessor subsystem up to 1.4 GHz |
| Cortex-A53 L2 Cache | 512 KB shared cache with SECDED ECC; quad-core Cortex-A53 cluster |
| Cortex-A53 L1 Data Cache | 32 KB per core with SECDED ECC; each Cortex-A53 core |
| Cortex-A53 L1 Instruction Cache | 32 KB per core with parity protection; each Cortex-A53 core |
| MCU Core | Single-core Arm Cortex-R5F up to 800 MHz; integrated as part of MCU channel with FFI |
| MCU Core Memory | 32 KB ICache, 32 KB L1 DCache, 64 KB TCM; SECDED ECC on all memories |
| MCU SRAM | 512 KB SRAM with SECDED ECC; Cortex-R5F MCU subsystem |
| Device Management Core | Single-core Arm Cortex-R5F up to 800 MHz; device management support |
| Deep Learning Accelerator | Single-core C7x with 256-bit vector DSP up to 40 GFLOPS; C7x floating point at 1.0 GHz |
| Matrix Multiply Accelerator | Up to 2 TOPS, 8-bit; MMA at 1.0 GHz |
| C7x Memory | 64 KB L1 DCache, 32 KB L1 ICache, 1.25 MB L2 SRAM; DCache and L2 SRAM with SECDED ECC; ICache with parity protection |
| Vision Processing Accelerator | 315 MPixel/s ISP, up to 5 MP at 60 fps; VPAC with image signal processor and vision assist accelerators |
| ISP Input Format | Up to 16-bit RAW input; 12-bit RGB-IR supported; vision processing accelerator ISP |
| ISP Line Support | Up to 4096; vision processing accelerator ISP |
| Display Support | Single display up to 2048 x 1080 at 60 fps; DPI 24-bit RGB parallel interface |
| Display Pixel Clock | Up to 165 MHz; independent PLL |
| Camera Interface | One CSI-2 receiver with 4-lane D-PHY; MIPI CSI-2 v1.3 compliant; MIPI D-PHY 1.2 |
| CSI-2 Lane Speed | Up to 2.5 Gbps per lane; supports 1, 2, 3, or 4 data lane mode |
| Video Codec | HEVC H.265 Main profile Level 5.1 High-tier; H.264 Baseline/Main/High Level 5.2; video encoder/decoder |
| Video Resolution | Up to 4K UHD, 3840 x 2160; video encoder/decoder and Motion JPEG encode |
| Motion JPEG Encode Rate | 416 MPixels/s; resolutions up to 4K UHD, 3840 x 2160 |
| On-Chip RAM | Up to 2.29 MB; total on-chip RAM across subsystems |
| DDR Interface | LPDDR4, 32-bit data bus with inline ECC; DDRSS |
| DDR Speed | Up to 3733 MT/s; LPDDR4 DDR subsystem |
| DDR Address Range | Maximum 8 GB; DDR subsystem addressable range |
| Ethernet | Integrated Ethernet switch with 2 external ports; RMII 10/100 or RGMII 10/100/1000; TSN support |
| USB | 2 USB 2.0 ports; configurable as host, peripheral, or dual-role device; integrated VBUS detection |
| UART Interfaces | 9 UARTs; general connectivity |
| SPI Interfaces | 5 SPI controllers; general connectivity |
| I2C Interfaces | 6 I2C ports; general connectivity |
| CAN Interfaces | 3 CAN modules with CAN-FD support; up to 64 data bytes; speed up to 8 Mbps |
| MMC/SD/SDIO | 3 interfaces: 1 eMMC up to HS200 and 2 SD/SDIO up to UHS-I; compliant with eMMC 5.1, SD 3.0, SDIO 3.0 |
| GPMC | 8-bit and 16-bit asynchronous memory interface up to 133 MHz; up to four chip selects; NAND, NOR, muxed-NOR, SRAM |
| OSPI/QSPI | DDR/SDR support with 4 GB memory address support; supports serial NAND and serial NOR flash; XIP mode with optional on-the-fly encryption |
| Boot Options | UART, I2C EEPROM, OSPI/QSPI flash, GPMC NOR/NAND, serial NAND, SD card, eMMC, USB host, USB device DFU, Ethernet |
| Technology Node | 16-nm FinFET; technology/package specification |
| Functional Safety | Systematic capability up to ASIL D targeted; hardware integrity up to ASIL B targeted; functional safety-compliant targeted automotive device |
| AEC Qualification | AEC-Q100 qualified; automotive variants |
| Security | Secure boot, hardware-enforced root of trust, backup key RoT switch, anti-rollback protection; security subsystem |
| Cryptographic Acceleration | AES 128/192/256, SHA2 224/256/384/512, DRBG with TRNG, PKA for RSA/ECC; cryptographic cores and secure boot acceleration |
| Datasheet Status | request_only |
Product Overview
Texas Instruments AM62A7 is a Sitara AI vision processor categorized here as a Microcontroller component. Its compute structure includes up to a quad 64-bit Arm Cortex-A53 application cluster running up to 1.4 GHz, a Cortex-R5F MCU channel up to 800 MHz, and a separate Cortex-R5F device management core. The C7x engine adds 256-bit vector DSP capability up to 40 GFLOPS, with an 8-bit matrix multiply accelerator rated up to 2 TOPS at 1.0 GHz.
Vision and media functions include a VPAC ISP rated at 315 MPixel/s, support for up to 5 MP at 60 fps, one 4-lane MIPI CSI-2 receiver, 4K UHD H.265/H.264 video codec support, and Motion JPEG encode at 416 MPixels/s. Display output supports a single 2048 x 1080 display at 60 fps through a 24-bit RGB parallel interface.
The device is available in AMB FCBGA and ANF FCCSP 484-pin, 18 mm x 18 mm, 0.8 mm pitch packages. System integration features include LPDDR4 with inline ECC, Ethernet with TSN support, USB 2.0, CAN-FD, MMC/SD/SDIO, GPMC, OSPI/QSPI, multiple boot sources, secure boot, cryptographic acceleration, and automotive-oriented functional safety targets.
Key Features
- Quad 64-bit Arm Cortex-A53 application processing up to 1.4 GHz
- Cortex-R5F MCU channel up to 800 MHz with ECC memories
- C7x vector DSP delivers up to 40 GFLOPS at 1.0 GHz
- 8-bit matrix multiply accelerator rated up to 2 TOPS
- VPAC ISP supports 315 MPixel/s and 5 MP at 60 fps
- One 4-lane MIPI CSI-2 receiver up to 2.5 Gbps per lane
- 4K UHD H.265 and H.264 video codec support
- LPDDR4 32-bit interface supports inline ECC up to 3733 MT/s
- Integrated Ethernet switch with two external TSN-capable ports
- Secure boot and hardware-enforced root of trust supported
Typical Applications
- AI vision processing
- Camera-based embedded systems
- 4K UHD video encode and decode
- Automotive vision platforms
- MIPI CSI-2 camera input systems
- Display systems up to 2048 x 1080
- Ethernet-connected industrial controllers
- CAN-FD connected embedded nodes
Procurement Notes
When requesting a quote for AM62A7, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What processor cores are integrated in AM62A7?
AM62A7 includes up to a quad 64-bit Arm Cortex-A53 application processor subsystem up to 1.4 GHz, a single-core Arm Cortex-R5F MCU core up to 800 MHz, and a single-core Arm Cortex-R5F device management core.
What AI acceleration capability does AM62A7 provide?
The device integrates a single-core C7x engine with a 256-bit vector DSP rated up to 40 GFLOPS at 1.0 GHz, plus an 8-bit matrix multiply accelerator rated up to 2 TOPS at 1.0 GHz.
Which camera and vision interfaces are supported by AM62A7?
AM62A7 supports one MIPI CSI-2 receiver with a 4-lane D-PHY, lane speeds up to 2.5 Gbps, and 1-, 2-, 3-, or 4-data-lane modes. The VPAC ISP supports 315 MPixel/s and up to 5 MP at 60 fps.
What memory interfaces are specified for AM62A7?
AM62A7 includes up to 2.29 MB of on-chip RAM and an LPDDR4 DDR subsystem with a 32-bit data bus, inline ECC, speeds up to 3733 MT/s, and a maximum 8 GB addressable DDR range.
What packages are listed for AM62A7?
The listed packages are AMB FCBGA 484-pin and ANF FCCSP 484-pin. Both are specified as 18 mm x 18 mm packages with 0.8 mm pitch.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.