Specifications
| Type | Description |
|---|---|
| Part Number | CC1352R |
| Manufacturer | Texas Instruments |
| Product Type | Multi-band wireless MCU |
| Category | Microcontroller |
| Component Type | MCU |
| Package Case | VQFN-48, 7.00 mm x 7.00 mm body |
| Main CPU | 48-MHz Arm Cortex-M4F processor; System CPU |
| CoreMark Score | 148; EEMBC CoreMark benchmark |
| Flash Memory | 352 KB; In-system programmable flash |
| ROM | 256 KB; For protocols and library functions |
| Cache SRAM | 8 KB; Alternatively available as general-purpose RAM |
| Ultra-Low Leakage SRAM | 80 KB; SRAM protected by parity |
| Sensor Controller SRAM | 4 KB; Ultra-low power sensor controller |
| Debug Interface | 2-pin cJTAG and JTAG; Debugging support |
| Supply Voltage Range | 1.8 V to 3.8 V; Recommended operating supply range stated in features |
| Package GPIO Count | 28 GPIOs; 7 mm x 7 mm RGZ VQFN48 package |
| General-Purpose Timers | 4 x 32-bit or 8 x 16-bit; Peripheral feature set |
| ADC Resolution and Rate | 12-bit, 200 kSamples/s, 8 channels; Peripheral ADC |
| Comparators | 2 comparators with internal reference DAC; 1 continuous-time comparator and 1 ultra-low-power comparator |
| UART Interfaces | 2 x UART; Serial peripherals |
| SSI Interfaces | 2 x SSI; Supports SPI, MICROWIRE, and TI modes |
| Cryptographic Accelerator | AES 128-bit and 256-bit; Hardware cryptographic accelerator |
| Public Key Accelerator | ECC and RSA; Hardware public key acceleration |
| SHA Accelerator | SHA2 full suite up to SHA-512; Hardware SHA2 accelerator |
| Random Number Generator | True random number generator; TRNG peripheral |
| Capacitive Sensing Channels | Up to 8 channels; Capacitive sensing peripheral |
| Active RX Current, 868 MHz | 5.8 mA; 3.6 V, 868 MHz |
| Active RX Current, 2.4 GHz | 6.9 mA; 3.0 V, 2.4 GHz |
| Active TX Current at 0 dBm, 868 MHz | 8.0 mA; 3.6 V, 868 MHz |
| Active TX Current at 0 dBm, 2.4 GHz | 7.1 mA; 3.0 V, 2.4 GHz |
| Active TX Current at +14 dBm | 24.9 mA; 868 MHz |
| Active MCU Current | 2.9 mA, 60 uA/MHz; 48 MHz CoreMark, 3.6 V |
| Sensor Controller Low-Power Current | 30.1 uA; 2 MHz, running infinite loop |
| Sensor Controller Active Current | 808 uA; 24 MHz, running infinite loop |
| Standby Current | 0.85 uA; RTC on, 80 KB RAM and CPU retention |
| Shutdown Current | 150 nA; Wakeup on external events |
| RF Bands | Sub-1 GHz and 2.4 GHz; Multi-band RF transceiver |
| Supported Bluetooth Version | Bluetooth 5.2 Low Energy and earlier LE specifications; Radio protocol support |
| IEEE 802.15.4 Support | IEEE 802.15.4 PHY and MAC; Radio protocol support |
| PTA Coexistence | 3-wire, 2-wire, 1-wire; Coexistence mechanisms |
| Receiver Sensitivity, Long-Range Mode | -121 dBm; SimpleLink long-range mode |
| Receiver Sensitivity, 50 kbps | -110 dBm; 50 kbps |
| Receiver Sensitivity, Bluetooth LE Coded PHY | -105 dBm; Bluetooth 125-kbps LE Coded PHY |
| Maximum Sub-1 GHz Output Power | +14 dBm; With temperature compensation |
| Maximum 2.4 GHz Output Power | +5 dBm; With temperature compensation |
| Supported ISM/SRD Bands | 169, 433, 470 to 510, 868, 902 to 928, and 2400 to 2480 MHz; ISM and SRD systems |
| Minimum Receive Bandwidth | Down to 4 kHz; ISM and SRD systems |
| 2.4 GHz TX Current at Maximum Power | 9.6 mA; +5 dBm transmit power at 2.4 GHz |
| Industrial High-Temperature Standby Current | 5 uA; 85°C standby current |
| Sensor Controller ADC Sampling Current | 1 uA system current; 1-Hz ADC sampling example |
| Orderable Part Number | CC1352R1F3RGZ; Device information table |
| Datasheet Status | request_only |
Product Overview
The CC1352R is a Texas Instruments multi-band wireless MCU built around a 48-MHz Arm Cortex-M4F system CPU with a 148 CoreMark score. Memory resources include 352 KB of in-system programmable flash, 256 KB ROM for protocols and library functions, 8 KB cache SRAM that can alternatively be used as general-purpose RAM, and 80 KB ultra-low leakage SRAM protected by parity.
The device combines MCU peripherals with a multi-band RF transceiver. It supports Sub-1 GHz and 2.4 GHz bands, Bluetooth 5.2 Low Energy and earlier LE specifications, IEEE 802.15.4 PHY and MAC, and 3-wire, 2-wire, or 1-wire PTA coexistence. Supported ISM/SRD bands include 169, 433, 470 to 510, 868, 902 to 928, and 2400 to 2480 MHz.
For assembly, the listed package is a VQFN-48 with a 7.00 mm x 7.00 mm body, and the 7 mm x 7 mm RGZ VQFN48 package provides 28 GPIOs. The peripheral set includes timers, ADC, comparators, UART, SSI, cryptographic acceleration, public key acceleration, SHA2 acceleration, TRNG, capacitive sensing, and low-power sensor controller operation.
Key Features
- 48-MHz Arm Cortex-M4F system CPU
- 352 KB in-system programmable flash memory
- 256 KB ROM for protocols and library functions
- Sub-1 GHz and 2.4 GHz RF transceiver
- Bluetooth 5.2 Low Energy radio protocol support
- IEEE 802.15.4 PHY and MAC support
- 12-bit ADC with 200 kSamples/s and 8 channels
- AES, ECC, RSA, SHA2, and TRNG hardware support
- 0.85 uA standby current with RTC and retention
- VQFN-48 package with 28 GPIOs
Typical Applications
- Bluetooth Low Energy wireless nodes
- IEEE 802.15.4 network devices
- Sub-1 GHz ISM systems
- 2.4 GHz ISM systems
- Low-power sensor controller designs
- Capacitive sensing interfaces
- Secure embedded wireless communication
- PTA coexistence wireless products
Procurement Notes
When requesting a quote for CC1352R, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What processor core does the CC1352R use?
The CC1352R uses a 48-MHz Arm Cortex-M4F processor as its system CPU. The extracted datasheet facts list a 148 score for the EEMBC CoreMark benchmark.
Which RF bands and protocols are supported by CC1352R?
The CC1352R includes a multi-band RF transceiver supporting Sub-1 GHz and 2.4 GHz operation. Protocol support includes Bluetooth 5.2 Low Energy and earlier LE specifications, plus IEEE 802.15.4 PHY and MAC.
What memory resources are integrated in the CC1352R?
The device includes 352 KB of in-system programmable flash, 256 KB ROM for protocols and library functions, 8 KB cache SRAM alternatively available as general-purpose RAM, 80 KB ultra-low leakage SRAM, and 4 KB sensor controller SRAM.
What package and GPIO count are listed for this device?
The listed package is VQFN-48 with a 7.00 mm x 7.00 mm body. The extracted facts specify 28 GPIOs for the 7 mm x 7 mm RGZ VQFN48 package.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.