Specifications
| Type | Description |
|---|---|
| Part Number | DRA829V |
| Manufacturer | Texas Instruments |
| Product Type | Automotive processor SoC |
| Category | Microcontroller |
| Package / Case | ALF (FCBGA, 827), 24.0 mm x 24.0 mm, 0.8-mm pitch |
| Architecture | Armv8 64-bit |
| Arm Cortex-A72 Microprocessor Subsystem | Dual core |
| Arm Cortex-A72 Maximum Frequency | Up to 2.0 GHz |
| Arm Cortex-A72 Shared L2 Cache | 1 MB per dual-core cluster |
| Arm Cortex-A72 L1 DCache | 32 KB per core |
| Arm Cortex-A72 L1 ICache | 48 KB per core |
| Arm Cortex-R5F MCU Cores | Hexa core |
| Arm Cortex-R5F Maximum Frequency | Up to 1.0 GHz |
| Arm Cortex-R5F Cache and TCM | 16 KB I-cache, 16 KB D-cache, 64 KB L2 TCM |
| Lockstep Support | Optional |
| C7x Floating Point Vector DSP | No |
| Deep Learning Accelerator MMA | No |
| C66x Floating Point DSP | No |
| Graphics Accelerator | No |
| Video Encoder/Decoder | No |
| Device Management Security Controller | Yes |
| Security Accelerators | Yes |
| Safety Targeted | Optional |
| Device Security | Optional |
| AEC-Q100 Qualification | Optional on Q1 variants |
| Main Domain On-Chip Shared Memory | 512 KB SRAM |
| MCU Domain On-Chip Shared Memory | 1 MB SRAM |
| Multicore Shared Memory Controller | 8 MB on-chip SRAM with ECC |
| LPDDR4 DDR Subsystem Capacity | Up to 8 GB, 32-bit data bus with inline ECC |
| LPDDR4 Speed | Up to 4266 MT/s |
| LPDDR4 Bandwidth | Up to 14.9 GB/s |
| GPMC Addressable Memory | Up to 1 GB with ECC |
| Display Subsystem | Yes |
| CSI2.0 RX Interfaces | 2 x 4-lane RX |
| CSI2.0 TX Interfaces | 1 x 4-lane TX |
| MCAN Interfaces | 16 with full CAN-FD support |
| GPIO Count | Up to 226 |
| I2C Interfaces | 10 |
| I3C Interfaces | 3 |
| ADC Modules | 2 |
| MCSPI Interfaces | 11 |
| MCASP Modules | 12 modules |
| eMMC Interface | eMMC 5.1, 8-bit MMCSD0 |
| UFS Interface | UFS 2.1, 2 lanes |
| SD/SDIO Interfaces | 2 x SD3.0/SDIO3.0, 4-bit |
| PCIe Controllers | Up to 4 PCIe Gen3 controllers, up to 2 lanes per controller |
| USB Interfaces | 2 x USB 3.0 dual-role device subsystems |
| Ethernet Switch | Integrated switch supporting up to 8 external ports |
| Process Technology | 16-nm FinFET |
| Device ID Register Value | 0x1380 |
| Speed Grade | T |
| Datasheet Status | request_only |
Product Overview
The DRA829V is a Texas Instruments automotive processor SoC categorized here as a Microcontroller. It uses an Armv8 64-bit architecture with a dual-core Arm Cortex-A72 microprocessor subsystem running up to 2.0 GHz, supported by 1 MB shared L2 cache per dual-core cluster, 32 KB L1 data cache per core, and 48 KB L1 instruction cache per core.
For MCU-class control functions, the device includes hexa-core Arm Cortex-R5F resources up to 1.0 GHz with 16 KB I-cache, 16 KB D-cache, and 64 KB L2 TCM. Optional lockstep support, optional safety-targeted configuration, optional device security, a device management security controller, and security accelerators are included in the extracted device comparison data.
The package is ALF FCBGA with 827 balls, 24.0 mm x 24.0 mm body size, and 0.8-mm pitch. System interfaces include LPDDR4, GPMC, CSI-2, display, MCAN, GPIO, I2C, I3C, ADC, MCSPI, MCASP, eMMC, UFS, SD/SDIO, PCIe Gen3, USB 3.0, and an integrated Ethernet switch supporting up to 8 external ports.
Key Features
- Armv8 64-bit automotive processor SoC architecture
- Dual-core Arm Cortex-A72 subsystem up to 2.0 GHz
- Hexa-core Arm Cortex-R5F MCU resources up to 1.0 GHz
- LPDDR4 subsystem supports up to 8 GB with inline ECC
- 16 MCAN interfaces with full CAN-FD support
- CSI-2 includes two 4-lane RX and one 4-lane TX
- Up to four PCIe Gen3 controllers
- Two USB 3.0 dual-role device subsystems
- Integrated Ethernet switch supports up to 8 external ports
- Device management security controller and security accelerators included
- Optional lockstep, safety-targeted, and device-security support
- ALF FCBGA 827 package, 24.0 mm x 24.0 mm
Typical Applications
- Automotive processor SoC designs
- CAN-FD gateway interfaces
- Display subsystem applications
- CSI-2 camera interface designs
- PCIe and USB expansion
- Ethernet switch systems
- LPDDR4 memory designs
- Safety-targeted variants
Procurement Notes
When requesting a quote for DRA829V, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What processor architecture does the DRA829V use?
The DRA829V uses Armv8 64-bit architecture. The extracted data lists a dual-core Arm Cortex-A72 microprocessor subsystem and hexa-core Arm Cortex-R5F MCU resources for the DRA829VM device comparison.
What memory interfaces are listed for DRA829V?
The device supports an LPDDR4 DDR subsystem up to 8 GB with a 32-bit data bus and inline ECC. Extracted facts also list up to 4266 MT/s LPDDR4 speed, up to 14.9 GB/s bandwidth, and GPMC addressable memory up to 1 GB with ECC.
Which automotive networking interfaces are included?
The extracted facts list 16 MCAN interfaces with full CAN-FD support and an integrated Ethernet switch supporting up to 8 external ports. The Ethernet ports support 2.5 Gb SGMII, 1 Gb SGMII/RGMII, and 100 Mb RMII.
Does DRA829V include graphics or video acceleration?
No. The extracted device comparison lists the graphics accelerator as No and the video encoder/decoder as No. It also lists C7x floating point vector DSP, deep learning accelerator MMA, and C66x floating point DSP as No.
What package is used for the DRA829V?
The listed package is ALF FCBGA with 827 balls. The package dimensions are 24.0 mm x 24.0 mm with 0.8-mm pitch, according to the extracted package-case information.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.