Specifications
| Type | Description |
|---|---|
| Part Number | SN74LVC1G374 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | SOT-23 (DBV) 6-pin; SC70 (DCK) 6-pin; YEP/YZP NanoStar/NanoFree packages |
| Logic Function | Single positive-edge-triggered D-type flip-flop with 3-state output; Q set to D on positive CLK transition when OE is low |
| Supply Voltage | 1.65-5.5 V; recommended operating range |
| Data Retention Supply Voltage | 1.5 V min; data retention only |
| Input Voltage | 0-5.5 V; recommended operating condition |
| Output Voltage | 0 to VCC; recommended operating condition |
| Operating Free-Air Temperature | -40 to 125 °C; recommended operating range |
| High-Level Input Voltage at VCC=1.65 V to 1.95 V | 0.65 x VCC min |
| High-Level Input Voltage at VCC=2.3 V to 2.7 V | 1.7 V min |
| High-Level Input Voltage at VCC=3 V to 3.6 V | 2 V min |
| High-Level Input Voltage at VCC=4.5 V to 5.5 V | 0.7 x VCC min |
| Low-Level Input Voltage at VCC=1.65 V to 1.95 V | 0.35 x VCC max |
| Low-Level Input Voltage at VCC=2.3 V to 2.7 V | 0.7 V max |
| Low-Level Input Voltage at VCC=3 V to 3.6 V | 0.8 V max |
| Low-Level Input Voltage at VCC=4.5 V to 5.5 V | 0.3 x VCC max |
| High-Level Output Current at VCC=1.65 V | -4 mA |
| High-Level Output Current at VCC=2.3 V | -8 mA |
| High-Level Output Current at VCC=3 V | -16 mA to -24 mA |
| High-Level Output Current at VCC=4.5 V | -32 mA |
| Low-Level Output Current at VCC=1.65 V | 4 mA |
| Low-Level Output Current at VCC=2.3 V | 8 mA |
| Low-Level Output Current at VCC=3 V | 16 mA to 24 mA |
| Low-Level Output Current at VCC=4.5 V | 32 mA |
| Input Transition Rise/Fall Rate at 1.8 V ±0.15 V or 2.5 V ±0.2 V | 20 ns/V max |
| Input Transition Rise/Fall Rate at 3.3 V ±0.3 V | 10 ns/V max |
| Input Transition Rise/Fall Rate at 5 V ±0.5 V | 5 ns/V max |
| High-Level Output Voltage, IOH=-100 µA, VCC=1.65 V to 5.5 V | VCC - 0.1 V min |
| High-Level Output Voltage, IOH=-4 mA, VCC=1.65 V | 1.2 V min |
| High-Level Output Voltage, IOH=-8 mA, VCC=2.3 V | 1.9 V min |
| High-Level Output Voltage, IOH=-16 mA, VCC=3 V | 2.4 V min |
| High-Level Output Voltage, IOH=-24 mA, VCC=3 V | 2.3 V min |
| High-Level Output Voltage, IOH=-32 mA, VCC=4.5 V | 3.8 V min |
| Low-Level Output Voltage, IOL=100 µA, VCC=1.65 V to 5.5 V | 0.1 V max |
| Low-Level Output Voltage, IOL=4 mA, VCC=1.65 V | 0.45 V max |
| Low-Level Output Voltage, IOL=8 mA, VCC=2.3 V | 0.3 V max |
| Low-Level Output Voltage, IOL=16 mA, VCC=3 V | 0.4 V max |
| Low-Level Output Voltage, IOL=24 mA, VCC=3 V | 0.55 V max at -40 to 85 °C; 0.65 V max at -40 to 125 °C |
| Low-Level Output Voltage, IOL=32 mA, VCC=4.5 V | 0.55 V max at -40 to 85 °C; 0.65 V max at -40 to 125 °C |
| Input Current | ±1 µA max at -40 to 85 °C; ±2 µA max at -40 to 125 °C; VI=5.5 V or GND, VCC=0 to 5.5 V |
| High-Impedance Output Current | ±5 µA max; VO=0 to 5.5 V |
| Power-Off Leakage Current | ±10 µA max; VI or VO=5.5 V, VCC=0 V |
| Supply Current | 10 µA max; VI=5.5 V or GND, IO=0, VCC=1.65 V to 5.5 V |
| Delta Supply Current | 500 µA max; one input at VCC - 0.6 V, other inputs at VCC or GND, VCC=3 V to 5.5 V |
| Input Capacitance | 3 pF typ; VI=VCC or GND, VCC=3.3 V |
| Output Capacitance | 6 pF typ; VO=VCC or GND, VCC=3.3 V |
| Clock Frequency at VCC=1.8 V ±0.15 V | 100 MHz min; -40 to 125 °C |
| Clock Frequency at VCC=2.5 V ±0.2 V | 125 MHz min; -40 to 125 °C |
| Clock Frequency at VCC=3.3 V ±0.3 V | 150 MHz min; -40 to 125 °C |
| Clock Frequency at VCC=5 V ±0.5 V | 175 MHz min; -40 to 125 °C |
| Clock Pulse Duration at VCC=1.8 V ±0.15 V | 3.3 ns min; CLK high or low |
| Clock Pulse Duration at VCC=2.5 V ±0.2 V | 3 ns min; CLK high or low |
| Clock Pulse Duration at VCC=3.3 V ±0.3 V | 2.8 ns min; CLK high or low |
| Clock Pulse Duration at VCC=5 V ±0.5 V | 2.5 ns min; CLK high or low |
| Setup Time at VCC=1.8 V ±0.15 V | 3.5 ns min; data before CLK rising edge |
| Setup Time at VCC=2.5 V ±0.2 V | 2.5 ns min; data before CLK rising edge |
| Setup Time at VCC=3.3 V ±0.3 V | 2 ns min; data before CLK rising edge |
| Setup Time at VCC=5 V ±0.5 V | 1.5 ns min; data before CLK rising edge |
| Hold Time at VCC=1.8 V ±0.15 V | 3.4 ns min; data after CLK rising edge |
| Hold Time at VCC=2.5 V ±0.2 V | 1.6 ns min; data after CLK rising edge |
| Hold Time at VCC=3.3 V ±0.3 V or 5 V ±0.5 V | 1.5 ns min; data after CLK rising edge |
| Propagation Delay, CLK to Q, CL=15 pF, VCC=1.8 V ±0.15 V | 2.5-15 ns; -40 to 85 °C |
| Propagation Delay, CLK to Q, CL=15 pF, VCC=2.5 V ±0.2 V | 2-6 ns; -40 to 85 °C |
| Propagation Delay, CLK to Q, CL=15 pF, VCC=3.3 V ±0.3 V | 1.4-4 ns; -40 to 85 °C |
| Propagation Delay, CLK to Q, CL=15 pF, VCC=5 V ±0.5 V | 1-3 ns; -40 to 85 °C |
| Propagation Delay, CLK to Q, CL=30 pF or 50 pF, VCC=1.8 V ±0.15 V | 2.7-18.3 ns; -40 to 125 °C |
| Propagation Delay, CLK to Q, CL=30 pF or 50 pF, VCC=2.5 V ±0.2 V | 1.8-10.2 ns; -40 to 125 °C |
| Propagation Delay, CLK to Q, CL=30 pF or 50 pF, VCC=3.3 V ±0.3 V | 1.6-7 ns; -40 to 125 °C |
| Propagation Delay, CLK to Q, CL=30 pF or 50 pF, VCC=5 V ±0.5 V | 1-5 ns; -40 to 125 °C |
| Output Enable Time | 0.9-6.5 ns; OE to Q, CL=30 pF or 50 pF, VCC=3.3 V ±0.3 V, -40 to 125 °C |
| Output Disable Time | 1.4-6 ns; OE to Q, CL=30 pF or 50 pF, VCC=3.3 V ±0.3 V, -40 to 125 °C |
| Power Dissipation Capacitance, Outputs Enabled at 1.8 V or 2.5 V | 24 pF typ; f=10 MHz, TA=25 °C |
| Power Dissipation Capacitance, Outputs Enabled at 3.3 V | 25 pF typ; f=10 MHz, TA=25 °C |
| Power Dissipation Capacitance, Outputs Enabled at 5 V | 27 pF typ; f=10 MHz, TA=25 °C |
| Power Dissipation Capacitance, Outputs Disabled at 1.8 V or 2.5 V | 8 pF typ; f=10 MHz, TA=25 °C |
| Power Dissipation Capacitance, Outputs Disabled at 3.3 V | 9 pF typ; f=10 MHz, TA=25 °C |
| Power Dissipation Capacitance, Outputs Disabled at 5 V | 11 pF typ; f=10 MHz, TA=25 °C |
| Absolute Maximum Supply Voltage | -0.5 to 6.5 V; over operating free-air temperature range |
| Absolute Maximum Input Voltage | -0.5 to 6.5 V; over operating free-air temperature range |
| Absolute Maximum Output Voltage | -0.5 to 6.5 V; output high-impedance or power-off state |
| Continuous Output Current | ±50 mA; absolute maximum rating |
| Continuous Current Through VCC or GND | ±100 mA; absolute maximum rating |
| Storage Temperature | -65 to 150 °C; absolute maximum rating |
| ESD Protection | 2000 V HBM, 200 V machine model, 1000 V charged-device model; JESD22 A114-A, A115-A, C101 |
| Latch-Up Performance | Exceeds 100 mA; JESD78 Class II |
| Thermal Impedance, DBV Package | 165 °C/W; JESD51-7 |
| Thermal Impedance, DCK Package | 259 °C/W; JESD51-7 |
| Thermal Impedance, YEP/YZP Package | 123 °C/W; JESD51-7 |
| Datasheet Status | request_only |
Product Overview
The SN74LVC1G374 is a Texas Instruments single D-type flip-flop for Signal_Chain logic functions. Its logic function is a single positive-edge-triggered D-type flip-flop with a 3-state output: Q is set to D on the positive CLK transition when OE is low. This supports clocked data storage and controlled output connection to a shared or isolated signal node.
Key Features
- Single positive-edge-triggered D-type flip-flop function
- 3-state output controlled by OE input
- Q follows D on positive CLK transition when OE is low
- 1.65-5.5 V recommended supply voltage range
- 1.5 V minimum supply for data retention
- 0-5.5 V recommended input voltage range
- -40 to 125 °C operating free-air temperature
- Up to 175 MHz minimum clock frequency at 5 V
- SOT-23, SC70, and NanoStar/NanoFree package options
- Power-off leakage current rated ±10 µA maximum
Typical Applications
- Clocked data storage
- 3-state output isolation
- Single-bit signal buffering
- Compact logic interfacing
- Data retention circuits
- Shared output-node control
- Positive-edge timing functions
Procurement Notes
When requesting a quote for SN74LVC1G374, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For MCU, processor and logic IC sourcing, package, operating voltage, temperature grade, speed or frequency grade, firmware or mask version, lifecycle status and programming requirements should be checked before approval.
FAQ
What logic function does SN74LVC1G374 provide?
SN74LVC1G374 provides a single positive-edge-triggered D-type flip-flop with a 3-state output. According to the extracted datasheet facts, Q is set to D on the positive CLK transition when OE is low.
What supply voltage range is recommended for this device?
The recommended operating supply range is 1.65-5.5 V. The extracted facts also list a 1.5 V minimum supply for data retention only, separate from the normal recommended operating range.
Which packages are listed for SN74LVC1G374?
The listed package options are SOT-23 (DBV) 6-pin, SC70 (DCK) 6-pin, and YEP/YZP NanoStar/NanoFree packages. Thermal impedance values are 165 °C/W for DBV, 259 °C/W for DCK, and 123 °C/W for YEP/YZP.
What timing limits are specified for clocked operation?
The timing facts list minimum clock frequencies from 100 MHz at 1.8 V ±0.15 V to 175 MHz at 5 V ±0.5 V. Setup time ranges from 3.5 ns minimum at 1.8 V to 1.5 ns minimum at 5 V.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.