Specifications
| Type | Description |
|---|---|
| Part Number | UCC27517 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Package / Case | SOT-23 (DBV), 5 pins, 2.90 mm × 1.60 mm |
| Component Type | Power_IC |
| Peak Source Current | 4 A; VDD = 12 V |
| Peak Sink Current | 4 A; VDD = 12 V |
| Supply Voltage Range | 4.5 to 18 V; recommended operating range |
| Nominal Supply Voltage | 12 V; recommended operating conditions |
| Propagation Delay | 13 ns typ; typical device operation |
| Rise Time | 9 ns typ; typical device operation |
| Fall Time | 7 ns typ; typical device operation |
| Operating Junction Temperature Range | -40 to 140 °C; recommended operating conditions |
| Absolute Maximum Supply Voltage | -0.3 to 20 V; over operating free-air temperature range |
| Absolute Maximum OUT Voltage | -0.3 to VDD + 0.3 V; DC |
| Absolute Maximum OUT Voltage, Pulsed | -2 to VDD + 0.3 V; repetitive pulse less than 200 ns |
| Output Continuous Current | 0.3 A; source/sink |
| Output Pulsed Current | 4 A; source/sink, 0.5 µs pulse |
| Input Pin Absolute Maximum Voltage | -0.3 to 20 V; IN+ and IN-; not restricted by VDD pin voltage |
| Operating Virtual Junction Temperature | -40 to 150 °C; absolute maximum rating |
| Storage Temperature | -65 to 150 °C; absolute maximum rating |
| Lead Temperature | 300 °C; soldering, 10 seconds |
| Reflow Temperature | 260 °C; absolute maximum rating |
| HBM ESD Rating | ±4000 V; ANSI/ESDA/JEDEC JS-001 |
| CDM ESD Rating | ±1000 V; JEDEC JESD22-C101 |
| Recommended Input Voltage | 0 to 18 V; IN+ and IN- |
| Junction-to-Ambient Thermal Resistance | 217.6 °C/W; UCC27517 SOT-23, 5 pins |
| Junction-to-Case Top Thermal Resistance | 85.8 °C/W; UCC27517 SOT-23, 5 pins |
| Junction-to-Board Thermal Resistance | 44.0 °C/W; UCC27517 SOT-23, 5 pins |
| Junction-to-Top Characterization Parameter | 4.0 °C/W; UCC27517 SOT-23, 5 pins |
| Junction-to-Board Characterization Parameter | 43.2 °C/W; UCC27517 SOT-23, 5 pins |
| Startup Current, Active Input State | 40 µA min, 100 µA typ, 160 µA max; VDD = 3.4 V, IN+ = VDD, IN- = GND |
| Startup Current, Equal Input States | 25 µA min, 75 µA typ, 145 µA max; VDD = 3.4 V, IN+ = IN- = GND or IN+ = IN- = VDD |
| Startup Current, Inverted Input State | 20 µA min, 60 µA typ, 115 µA max; VDD = 3.4 V, IN+ = GND, IN- = VDD |
| UVLO Supply Start Threshold, 25 °C | 3.91 V min, 4.20 V typ, 4.5 V max; TA = 25 °C |
| UVLO Supply Start Threshold, Full Temperature | 3.70 V min, 4.20 V typ, 4.65 V max; TA = -40 °C to 140 °C |
| UVLO Minimum Operating Voltage After Supply Start | 3.45 V min, 3.9 V typ, 4.35 V max; VDD falling |
| UVLO Supply Voltage Hysteresis | 0.2 V min, 0.3 V typ, 0.5 V max; VDD UVLO |
| Input Signal High Threshold | 2.2 V min, 2.4 V max; output high for IN+ pin, output low for IN- pin |
| Input Signal Low Threshold | 1.0 V min, 1.2 V max; output low for IN+ pin, output high for IN- pin |
| Input Signal Hysteresis | 1.0 V typ; IN+ and IN- |
| Source/Sink Peak Current | ±4 A; CLOAD = 0.22 µF, FSW = 1 kHz |
| High Output Voltage Drop, 12 V | 50 mV typ, 90 mV max; VDD = 12 V, IOUT = -10 mA |
| High Output Voltage Drop, 4.5 V | 60 mV typ, 130 mV max; VDD = 4.5 V, IOUT = -10 mA |
| Low Output Voltage, 12 V | 5 mV typ, 10 mV max; VDD = 12 V, IOUT = 10 mA |
| Low Output Voltage, 4.5 V | 6 mV typ, 12 mV max; VDD = 4.5 V, IOUT = 10 mA |
| Output Pullup Resistance, 12 V | 5.0 Ω typ, 7.5 Ω max; VDD = 12 V, IOUT = -10 mA |
| Output Pullup Resistance, 4.5 V | 5.0 Ω typ, 11.0 Ω max; VDD = 4.5 V, IOUT = -10 mA |
| Output Pulldown Resistance, 12 V | 0.5 Ω typ, 1.0 Ω max; VDD = 12 V, IOUT = 10 mA |
| Output Pulldown Resistance, 4.5 V | 0.6 Ω typ, 1.2 Ω max; VDD = 4.5 V, IOUT = 10 mA |
| Input Logic Compatibility | TTL and CMOS compatible; input thresholds independent of VDD supply voltage |
| Output State During UVLO | held low; during VDD undervoltage lockout, power-up, and power-down |
| Input Configuration | dual input, inverting IN- or noninverting IN+; unused input can be used for enable or disable function |
| Floating Input Behavior | output held low; input pins floating or unbiased |
| Datasheet Status | request_only |
Product Overview
The UCC27517 is a Texas Instruments single-channel low-side gate driver for Power_Management designs. It provides 4 A peak source current and 4 A peak sink current at VDD = 12 V, with ±4 A source/sink peak current specified using CLOAD = 0.22 µF at FSW = 1 kHz. The recommended supply range is 4.5 to 18 V, with 12 V listed as the nominal supply condition.
Key Features
- 4 A peak source current at VDD = 12 V
- 4 A peak sink current at VDD = 12 V
- 4.5 to 18 V recommended supply voltage range
- 13 ns typical propagation delay
- 9 ns typical rise time and 7 ns typical fall time
- TTL and CMOS compatible input thresholds
- Dual inverting or noninverting input configuration
- Output held low during UVLO and floating inputs
- ±4000 V HBM and ±1000 V CDM ESD ratings
- 5-pin SOT-23 package, 2.90 mm × 1.60 mm
Typical Applications
- Low-side MOSFET gate drive
- Single-channel power switch control
- TTL or CMOS driven gate stages
- PWM power stage drive
- UVLO-controlled output drive
- Compact SOT-23 power designs
Procurement Notes
When requesting a quote for UCC27517, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What supply voltage range does the UCC27517 support?
The UCC27517 has a recommended supply voltage range of 4.5 to 18 V, with 12 V listed as the nominal supply voltage under recommended operating conditions.
What are the peak drive current ratings?
The device is specified for 4 A peak source current and 4 A peak sink current at VDD = 12 V. A ±4 A source/sink peak current condition is also listed with CLOAD = 0.22 µF and FSW = 1 kHz.
How does the output behave during undervoltage lockout?
During VDD undervoltage lockout, power-up, and power-down, the UCC27517 output is held low. The extracted facts also state that floating or unbiased input pins hold the output low.
What input logic types are compatible with UCC27517?
The input logic is TTL and CMOS compatible, and the input thresholds are independent of the VDD supply voltage. The device provides dual input control using inverting IN- or noninverting IN+.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.