UCC27714 600-V Half-Bridge Gate Driver

Texas Instruments Power_Management — specifications, applications, sourcing support and RFQ.

UCC27714 600-V Half-Bridge Gate Driver

RFQ Available Sourcing Support Alternative Matching RoHS
Part Number
UCC27714
Manufacturer
Texas Instruments
Package
SOIC-14, body size 3.91 mm x 8.65 mm
Category
Power Management
Product Type
LDO Regulator

Quick Sourcing Note

UCC27714 from Texas Instruments is a Power_Management 600-V half-bridge gate driver supplied in a 14-pin SOIC package with a 3.91 mm x 8.65 mm body. It supports 600 V HS pin operation and 4 A peak source and sink current on HO and LO outputs at VDD = 15 V. Recommended operation includes 10-17 V VDD and 10-17 V HB-HS bootstrap voltage, with -40 to 125 °C recommended junction temperature. Timing data includes 90 ns typical turn-on and turn-off propagation delays, 15 ns typical rise and fall times with a 1000-pF load, and 20 ns maximum delay matching.

Specifications

TypeDescription
Part NumberUCC27714
ManufacturerTexas Instruments
Product TypeLDO Regulator
CategoryPower Management
Package / CaseSOIC-14, body size 3.91 mm x 8.65 mm
Component TypePower_IC
High-side voltage rating600 V; HS pin operation
Peak output source current4 A; VDD=15 V, HO/LO outputs
Peak output sink current4 A; VDD=15 V, HO/LO outputs
VDD bias supply range10-20 V; device description/features
Recommended VDD supply voltage10-17 V; recommended operating conditions
Recommended driver bootstrap voltage10-17 V; HB-HS, recommended operating conditions
Recommended HS source terminal voltage-8 to 600 V; logic operational at HB-HS=12 V
Recommended HB bootstrap pin voltageHS+10 to HS+17 V; recommended operating conditions
Recommended input voltage-4 to 17 V; HI, LI, EN with respect to VSS
Recommended VSS logic ground voltage-6 to 5 V; -6 V at VDD-COM=10 V; 5 V at VDD-COM=15 V
Recommended junction temperature-40 to 125 °C; recommended operating conditions
Absolute maximum HI/LI/EN voltage-5 to 20 V; with respect to VSS
Absolute maximum VDD supply voltage-0.3 to 20 V; with respect to COM
Absolute maximum HB voltage-0.3 to 640 V; input voltage range
Absolute maximum HB-HS voltage-0.3 to 20 V; input voltage range
Absolute maximum HO DC output voltageHS-0.3 to HB+0.3 V; DC output voltage range
Absolute maximum HO transient output voltageHS-2 to HB+0.3 V; transient less than 100 ns
Absolute maximum LO DC output voltage-0.3 to VDD+0.3 V; DC output voltage range
Absolute maximum LO transient output voltage-2 to VDD+0.3 V; transient less than 100 ns
Absolute maximum VSS to COM voltage-7 to 6 V; logic ground with respect to COM
Absolute maximum VDD-VSS voltage-0.3 to 20 V; logic ground, VDD-VSS
Absolute maximum pulsed output current±4 A; HO, LO, IOUT_PULSED, 100 ns
Absolute maximum DC output current0.25 A; HO, LO, IOUT_DC
Allowable HS offset supply transient-50 to 50 V/ns; dVHS/dt
Junction temperature absolute maximum-40 to 150 °C; absolute maximum ratings
Storage temperature range-65 to 150 °C; absolute maximum ratings
ESD rating HBM±1400 V; human body model
ESD rating CDM±500 V; charged device model
Junction-to-ambient thermal resistance72.3 °C/W; D package SOIC-14
Junction-to-case top thermal resistance31.8 °C/W; D package SOIC-14
Junction-to-board thermal resistance26.5 °C/W; D package SOIC-14
VDD turn-on threshold8.4 min, 9.1 typ, 9.8 max V; VDD(on)
VDD turn-off threshold7.9 min, 8.6 typ, 9.3 max V; VDD(off)
VDD UVLO hysteresis0.4 min, 0.5 typ V; VDD(hys)
HB-HS turn-on threshold7.7 min, 8.3 typ, 9.0 max V; VHB(on)-VHS
HB-HS turn-off threshold6.7 min, 7.25 typ, 8.05 max V; VHB(off)-VHS
HB-HS UVLO hysteresis0.5 min, 1.0 typ V; VHB(hys)
Total quiescent supply current750 typ, 1050 max µA; HI=LI=0 V or 5 V, DC on/off state
VDD-COM quiescent supply current175 typ, 350 max µA; HI=LI=0 V or 5 V, DC on/off state
VDD-VSS quiescent supply current550 typ, 750 max µA; HI=LI=0 V or 5 V, DC on/off state
HB-HS quiescent supply current120 typ, 300 max µA; HI=0 V or 5 V, HO in DC on/off state
Bootstrap supply leakage current20 max µA; HB=HS=600 V
Input and enable high threshold1.7 min, 2.3 typ, 2.7 max V; HI, LI, EN high threshold
Input and enable low threshold1.2 min, 1.6 typ, 2.1 max V; HI, LI, EN low threshold
Input and enable threshold hysteresis0.7 typ V; HI, LI, EN
HI/LI input low bias current-5 min, 0 typ, 5 max µA; HI, LI=0 V
HI/LI input high bias current3 typ, 65 max µA; HI, LI=5 V
EN input low bias current-90 min, -50 typ µA; VEN=0 V
EN input high bias current-65 min, -25 typ µA; VEN=5 V
HI pull-down resistance400 kΩ; HI input pin
LI pull-down resistance400 kΩ; LI input pin
EN pull-up resistance200 kΩ; enable pin
LO output high voltage drop70 typ, 120 max mV; VDD-VLOH, LI=5 V, ILO=-20 mA
HO output high voltage drop70 typ, 120 max mV; VHB-VHOH, HI=5 V, IHO=-20 mA
LO output low voltage15 typ, 35 max mV; LI=0 V, ILO=20 mA
HO output low voltage20 typ, 40 max mV; HI=0 V, IHO=20 mA
Output pull-down resistance1.45 typ Ω; LO/HO, ILO=20 mA, IHO=20 mA
Output pull-up resistance3.75 typ, 5.8 max Ω; LO/HO, ILO=-20 mA, IHO=-20 mA
Output low short-circuit pulsed current4 A; HI=LI=0 V, HO=LO=15 V, pulse width <10 µs; ensured by design
Output high short-circuit pulsed current4 A; HI=LI=5 V, HO=LO=0 V, pulse width <10 µs; ensured by design
Turn-on propagation delay90 typ, 125 max ns; LI to LO, HI to HO, HS=COM=0 V or HS=600 V
Turn-off propagation delay90 typ, 125 max ns; LI to LO, HI to HO, HS=COM=0 V or HS=600 V
Low-to-high delay matching20 max ns; HS=COM=0 V
High-to-low delay matching20 max ns; HS=COM=0 V
Output rise time15 typ, 30 max ns; 10% to 90%, HO/LO with 1000-pF load
Output fall time15 typ, 30 max ns; 90% to 10%, HO/LO with 1000-pF load
Minimum HI/LI on pulse width40 nom, 100 max ns; 0-V to 5-V input signal on HI and LI pins changes output state
Minimum HI/LI off pulse width40 nom, 100 max ns; 5-V to 0-V input signal on HI and LI pins changes output state
Pin count14 pins; D package SOIC
Enable functionLOW disables HO and LO; HIGH or floating enables HO and LO; EN/NC pin 4
Input floating behaviorHO and LO held low when inputs floating; HI and LI input pins
Datasheet Statusrequest_only

Product Overview

The UCC27714 is a Texas Instruments 600-V half-bridge gate driver for Power_Management designs using separate high-side and low-side gate-drive outputs. The HS pin supports 600 V operation, while HO and LO provide 4 A peak source and 4 A peak sink current at VDD = 15 V.

Key Features

  • 600 V HS pin operating rating
  • 4 A peak source and sink output current
  • 10-17 V recommended VDD supply voltage
  • 10-17 V recommended HB-HS bootstrap voltage
  • -8 to 600 V recommended HS terminal range
  • 90 ns typical turn-on and turn-off delays
  • 15 ns typical rise and fall times
  • 20 ns maximum propagation delay matching
  • HI and LI floating inputs hold outputs low
  • EN low disables both HO and LO

Typical Applications

  • 600-V half-bridge gate drive
  • High-side and low-side switching stages
  • Bootstrap-supplied high-side drive
  • Power_Management gate-driver designs
  • HO and LO MOSFET drive
  • Logic-controlled half-bridge outputs

Procurement Notes

When requesting a quote for UCC27714, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.

If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.

For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.

FAQ

What output current does the UCC27714 provide?

The UCC27714 provides 4 A peak source current and 4 A peak sink current on the HO and LO outputs when operated at VDD = 15 V.

What supply range is recommended for UCC27714 operation?

Recommended operating conditions list VDD at 10-17 V and the HB-HS driver bootstrap voltage at 10-17 V. The broader VDD bias supply range stated in the device facts is 10-20 V.

How does the enable input control the outputs?

For the EN/NC pin, a LOW level disables both HO and LO. A HIGH level or a floating enable input enables the HO and LO outputs.

What happens when HI and LI inputs are floating?

The extracted device facts state that HO and LO are held low when the HI and LI input pins are floating.

Technical Review & Sourcing Note

Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.

This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.

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