Specifications
| Type | Description |
|---|---|
| Part Number | UCC28C42 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Package / Case | SOIC-8 (D), 3.91 mm x 4.90 mm nominal body size |
| Component Type | Power_IC |
| Controller topology | Fixed-frequency peak current-mode PWM controller; condition: device family description; source page 1 |
| Maximum operating frequency | 1 MHz; condition: features list; source page 1 |
| Startup current | 50 µA typ, 100 µA max; condition: features list; source page 1 |
| Operating current | 2.3 mA; condition: fOSC = 52 kHz; source page 1 |
| Current-sense-to-output delay | 35 ns; condition: cycle-by-cycle overcurrent limiting; source page 1 |
| Peak output drive current | ±1 A; condition: OUT driver peak source/sink current; source page 1 |
| Output rise time | 25 ns; condition: rail-to-rail output driver; source page 1 |
| Output fall time | 20 ns; condition: rail-to-rail output driver; source page 1 |
| Error amplifier reference accuracy | ±1%; condition: internal 2.5 V error amplifier reference; source page 1 |
| Error amplifier non-inverting input reference | 2.5 V ±1%; condition: FB pin description; source page 4 |
| UVLO turn-on threshold | 14.5 V; condition: UCC28C42, off-line applications; source page 3 |
| UVLO turn-off threshold | 9 V; condition: UCC28C42, off-line applications; source page 3 |
| Maximum duty cycle | 100%; condition: UCC28C42 device comparison table; source page 3 |
| Operating junction temperature | -40 to 125 °C; condition: UCC28C42 / UCC28C4x; source page 3 |
| Pin count | 8 pins; condition: SOIC package; source page 4 |
| COMP pin function | Error amplifier output for compensation and control port; condition: pin 1; source page 4 |
| FB pin function | Inverting input to error amplifier; condition: pin 2; source page 4 |
| CS pin function | Primary-side current sense, non-inverting input to PWM comparator; condition: pin 3; source page 4 |
| RT/CT pin function | Fixed-frequency oscillator set point; condition: pin 4, timing resistor to VREF and timing capacitor to GND; source page 4 |
| GND pin function | Ground return for output driver and logic controller; condition: pin 5; source page 4 |
| OUT pin function | MOSFET gate driver output; condition: pin 6; source page 4 |
| VDD pin function | Analog controller bias input; condition: pin 7; source page 4 |
| VREF pin function | 5 V reference output; condition: pin 8; source page 4 |
| OUT switching frequency | fSW = fOSC; condition: UCCx8C42 gate drive output; source page 4 |
| VDD bypass capacitance | 0.1 µF typical minimum local bypass; condition: VDD pin, connected directly to GND with minimal trace length; source page 4 |
| VREF bypass capacitance | 0.1 µF minimum ceramic; condition: VREF pin, connected close to pin to GND; source page 4 |
| Absolute maximum VDD input voltage | 20 V max; condition: absolute maximum ratings; source page 5 |
| Absolute maximum IVDD input current | 30 mA max; condition: absolute maximum ratings; source page 5 |
| Absolute maximum output drive current | ±1 A; condition: peak, absolute maximum ratings; source page 5 |
| Absolute maximum output energy | 5 µJ; condition: capacitive load, EOUT; source page 5 |
| Absolute maximum analog input voltage | -0.3 to 6.3 V; condition: COMP, CS, FB, RT/CT pins; source page 5 |
| Absolute maximum OUT voltage | -0.3 to 20 V; condition: output driver voltage; source page 5 |
| Absolute maximum VREF voltage | 7 V max; condition: reference voltage; source page 5 |
| Absolute maximum COMP sink current | 10 mA max; condition: error amplifier output sink current; source page 5 |
| Lead soldering temperature | 300 °C max; condition: 10 s soldering; source page 5 |
| Absolute operating junction temperature | -55 to 150 °C; condition: absolute maximum ratings; source page 5 |
| Storage temperature | -65 to 150 °C; condition: absolute maximum ratings; source page 5 |
| HBM ESD rating | ±2500 V; condition: ANSI/ESDA/JEDEC JS-001; source page 6 |
| CDM ESD rating | ±1500 V; condition: JEDEC JESD22-C101; source page 6 |
| Recommended VDD input voltage | 18 V max; condition: recommended operating conditions; source page 6 |
| Recommended OUT voltage | 18 V max; condition: recommended operating conditions; source page 6 |
| VREF external continuous voltage | 5.5 V max; condition: maximum continuous voltage from external circuitry; source page 6 |
| Average output driver current | 200 mA max; condition: source and sink, recommended operating conditions; source page 6 |
| Reference output current | 20 mA max; condition: source current, recommended operating conditions; source page 6 |
| SOIC junction-to-ambient thermal resistance | 128.9 °C/W; condition: D package, RθJA; source page 7 |
| SOIC junction-to-case top thermal resistance | 71.7 °C/W; condition: D package, RθJC(top); source page 7 |
| SOIC junction-to-board thermal resistance | 72.3 °C/W; condition: D package, RθJB; source page 7 |
| SOIC junction-to-top characterization parameter | 23.4 °C/W; condition: D package, ψJT; source page 7 |
| SOIC junction-to-board characterization parameter | 71.5 °C/W; condition: D package, ψJB; source page 7 |
| VREF initial accuracy | 4.9 V min, 5 V typ, 5.1 V max; condition: TJ = 25 °C, IOUT = 1 mA, VDD = 15 V; source page 7 |
| VREF line regulation | 0.2 mV typ, 20 mV max; condition: VDD = 12 V to 18 V; source page 7 |
| VREF load regulation | 3 mV typ, 25 mV max; condition: IOUT = 1 mA to 20 mA; source page 7 |
| VREF temperature stability | 0.2 mV/°C typ, 0.4 mV/°C max; condition: electrical characteristics note condition; source page 7 |
| VREF total output variation | 4.82 V min, 5.18 V max; condition: electrical characteristics note condition; source page 7 |
| VREF noise voltage | 50 µV typ; condition: 10 Hz to 10 kHz, TJ = 25 °C; source page 7 |
| VREF long-term stability | 5 mV typ, 25 mV max; condition: 1000 hours, TJ = 125 °C; source page 7 |
| VREF short-circuit source current | 30 mA min, 45 mA typ, 55 mA max; condition: output short circuit; source page 7 |
| Oscillator initial accuracy | 50.5 kHz min, 53 kHz typ, 55 kHz max; condition: TJ = 25 °C, RT = 10 kΩ, CT = 3.3 nF; source page 7 |
| Oscillator voltage stability | 0.2% typ, 1% max; condition: 12 V <= VDD <= 18 V; source page 7 |
| Oscillator temperature stability | 1% typ, 2.5% max; condition: TJ(min) to TJ(max); source page 7 |
| RT/CT oscillator amplitude | 1.9 V peak-to-peak; condition: RT/CT pin; source page 7 |
| Oscillator discharge current | 7.7 mA min, 8.4 mA typ, 9 mA max; condition: TJ = 25 °C, VRT/CT = 2 V; source page 7 |
| Oscillator discharge current over temperature | 7.2 mA min, 8.4 mA typ, 9.5 mA max; condition: VRT/CT = 2 V; source page 7 |
| Datasheet Status | request_only |
Product Overview
The Texas Instruments UCC28C42 is a fixed-frequency peak current-mode PWM controller in the Power_Management category. It uses a current-sense input as the non-inverting input to the PWM comparator, with the OUT switching frequency equal to the oscillator frequency. The RT/CT pin sets the fixed-frequency oscillator using a timing resistor to VREF and a timing capacitor to GND.
The controller integrates a 2.5 V ±1% error-amplifier reference at the FB input and provides COMP as the error-amplifier output for compensation and control. The OUT pin is a MOSFET gate-driver output with ±1 A peak source/sink capability, 25 ns rise time, and 20 ns fall time. Cycle-by-cycle overcurrent limiting is supported by a 35 ns current-sense-to-output delay.
The UCC28C42 is specified for off-line applications with 14.5 V UVLO turn-on and 9 V UVLO turn-off thresholds. The device is offered in an 8-pin SOIC package with a 3.91 mm x 4.90 mm nominal body size. Local bypassing is specified with 0.1 µF typical minimum on VDD and at least 0.1 µF ceramic capacitance on VREF close to GND.
Key Features
- Fixed-frequency peak current-mode PWM control topology
- Supports oscillator operation up to 1 MHz
- 50 µA typical startup current, 100 µA maximum
- 2.3 mA operating current at 52 kHz fOSC
- 35 ns current-sense-to-output delay for overcurrent limiting
- ±1 A peak OUT source and sink drive
- 25 ns output rise time and 20 ns fall time
- 2.5 V ±1% error-amplifier input reference
- 14.5 V turn-on and 9 V turn-off UVLO
- 100% maximum duty cycle for UCC28C42
Typical Applications
- Off-line PWM controller circuits
- Primary-side current-sense converters
- MOSFET gate-drive power stages
- Fixed-frequency power converters
- Cycle-by-cycle overcurrent-limited supplies
- SOIC-8 power-management designs
Procurement Notes
When requesting a quote for UCC28C42, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What type of controller is the UCC28C42?
The UCC28C42 is a Texas Instruments fixed-frequency peak current-mode PWM controller. It uses primary-side current sensing through the CS pin and drives a MOSFET gate through the OUT pin.
What UVLO thresholds apply to the UCC28C42?
For off-line applications, the UCC28C42 has a 14.5 V UVLO turn-on threshold and a 9 V UVLO turn-off threshold. The recommended VDD input voltage is specified up to 18 V.
What package and pin count does UCC28C42 use?
The UCC28C42 is listed in an SOIC-8 D package with 8 pins and a nominal body size of 3.91 mm x 4.90 mm.
What output drive capability is specified for UCC28C42?
The OUT pin is a MOSFET gate-driver output. The specified peak output drive current is ±1 A, with 25 ns rise time and 20 ns fall time for the rail-to-rail output driver.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.