Specifications
| Type | Description |
|---|---|
| Part Number | DS90C365A |
| Manufacturer | Texas Instruments |
| Product Type | LVDS Transmitter |
| Category | Signal Chain |
| Package / Case | 48-lead TSSOP, DS90C365ADGG0048A |
| Supply Voltage | 3.0 min, 3.3 nom, 3.6 max V; recommended operating condition, VCC |
| Operating Free-Air Temperature | -10 min, +25 nom, +70 max °C; recommended operating condition, TA |
| Supply Noise Voltage | 200 mVPP max; recommended operating condition, VCC noise |
| TxCLKIN Frequency | 18 min, 85 max MHz; recommended operating condition |
| Maximum Supported Shift Clock | 87.5 MHz; feature description |
| Input Data Width | 21 bits; 18-bit RGB plus 3 LCD timing/control inputs |
| LVDS Data Streams | 4 streams; converted from LVCMOS/LVTTL input data |
| LVDS Data Rate per Channel | 612.5 Mbps; Tx clock frequency = 87.5 MHz |
| Total Throughput | Up to 1.785 Gbps; feature description |
| Bandwidth | Up to 223.125 MB/s; feature description |
| High-Level Input Voltage | 2.0 min, VCC max V; LVCMOS/LVTTL DC specification, VIH |
| Low-Level Input Voltage | 0 min, 0.8 max V; LVCMOS/LVTTL DC specification, VIL |
| Input Clamp Voltage | -0.79 typ, -1.5 max V; ICL = -18 mA, VCL |
| Input Current | +1.8 typ, +10 max µA; VIN = 0.4 V, 2.5 V, or VCC |
| Differential Output Voltage | 250 min, 345 typ, 450 max mV; RL = 100 ohm, VOD |
| Offset Voltage | 1.13 min, 1.25 typ, 1.38 max V; LVDS DC specification, VOS |
| Power-Down Supply Current | 11 typ, 150 max µA; PowerDown = Low, driver outputs in TRI-STATE, ICCTZ |
| ESD Rating HBM | 7 kV; 1.5 kohm, 100 pF |
| ESD Rating EIAJ | 500 V; 0 ohm, 200 pF |
| Latch-Up Tolerance | ±100 mA; TA = 25°C |
| Storage Temperature | -65 to +150 °C; absolute maximum rating |
| Junction Temperature | +150 °C; absolute maximum rating |
| Datasheet Status | request_only |
Product Overview
The DS90C365A is a Texas Instruments LVDS flat panel transmitter in the Signal Chain category. It accepts 21 bits of LVCMOS/LVTTL input data, covering 18-bit RGB plus three LCD timing/control inputs, and converts that bus into four LVDS data streams for display-panel interconnects.
Recommended operation is based on a 3.0 V to 3.6 V supply with 3.3 V nominal VCC, a -10°C to +70°C free-air temperature range, and TxCLKIN operation from 18 MHz to 85 MHz. The device description also specifies a maximum supported shift clock of 87.5 MHz, 612.5 Mbps LVDS data rate per channel at that clock, up to 1.785 Gbps total throughput, and up to 223.125 MB/s bandwidth.
The listed package is a 48-lead TSSOP, DS90C365ADGG0048A. Input pins are compatible with LVCMOS and LVTTL levels but are not 5 V tolerant, so interface voltage must stay within the stated input limits. The R_FB pin selects falling-edge strobe when tied to GND or left unconnected, and rising-edge strobe when tied to VCC. When PWRDOWN is asserted low, the LVDS outputs enter TRI-STATE.
Key Features
- 21-bit input for 18-bit RGB plus LCD control
- Converts LVCMOS/LVTTL inputs into four LVDS streams
- Supports up to 87.5 MHz shift clock operation
- 612.5 Mbps LVDS data rate per channel at 87.5 MHz
- Up to 1.785 Gbps total throughput
- 3.0 V to 3.6 V recommended VCC range
- LVCMOS and LVTTL compatible input pins
- Inputs and control pins are not 5 V tolerant
- Programmable rising or falling strobe edge selection
- PWRDOWN low places outputs in TRI-STATE
Typical Applications
- LVDS flat panel links
- 18-bit RGB LCD interfaces
- LCD timing and control links
- 3.3 V display signal chains
- Spread-spectrum display clock designs
- LVCMOS/LVTTL to LVDS conversion
- Power-down controlled panel transmitters
Procurement Notes
When requesting a quote for DS90C365A, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the DS90C365A?
The DS90C365A is a Texas Instruments LVDS flat panel transmitter. It converts 21 bits of LVCMOS/LVTTL input data, including 18-bit RGB and three LCD timing/control signals, into four LVDS data streams.
What supply voltage range does DS90C365A use?
The recommended VCC operating range is 3.0 V minimum, 3.3 V nominal, and 3.6 V maximum. The listed supply noise limit under recommended operating conditions is 200 mVPP maximum.
What clock rates are specified for DS90C365A?
The recommended TxCLKIN frequency range is 18 MHz to 85 MHz. The device feature description lists a maximum supported shift clock of 87.5 MHz, with 612.5 Mbps LVDS data rate per channel at that clock.
Are DS90C365A inputs tolerant of 5 V logic?
No. The extracted datasheet facts state that the transmitter input and control inputs are not 5 V tolerant. The inputs are specified as LVCMOS and LVTTL compatible within the stated voltage limits.
What happens when PWRDOWN is asserted low?
When the PWRDOWN input is asserted low, the DS90C365A driver outputs enter TRI-STATE. The power-down supply current is specified as 11 µA typical and 150 µA maximum with PowerDown low.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.