Specifications
| Type | Description |
|---|---|
| Part Number | DS90C387 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 100 TQFP |
| Supply Voltage | 3.0 min, 3.3 typ, 3.6 max V; recommended operating conditions |
| Operating Free Air Temperature | -10 min, +25 typ, +70 max °C; recommended operating conditions |
| Receiver Input Range | 0 min, 2.4 max V; recommended operating conditions |
| Supply Noise Voltage | 100 max mV p-p; recommended operating conditions |
| Absolute Maximum Supply Voltage | -0.3 to +4 V; absolute maximum ratings |
| Absolute Maximum CMOS/TTL Input Voltage | -0.3 to +5.5 V; absolute maximum ratings |
| Absolute Maximum CMOS/TTL Output Voltage | -0.3 to VCC+0.3 V; absolute maximum ratings |
| Absolute Maximum LVDS Driver Output Voltage | -0.3 to +3.6 V; absolute maximum ratings |
| Junction Temperature | +150 °C; absolute maximum ratings |
| Storage Temperature | -65 to +150 °C; absolute maximum ratings |
| Package Power Dissipation | 2.8 W; TA=25°C, 100 TQFP package, DS90C387 |
| Package Derating | 18.2 mW/°C above +25°C; 100 TQFP package, DS90C387 |
| ESD Rating HBM | >6 kV; HBM, 1.5 kΩ, 100 pF, DS90C387 |
| ESD Rating EIAJ | >300 V; EIAJ, 0 Ω, 200 pF, DS90C387 |
| High Level Input Voltage | 2.0 min, 5.0 max V; CMOS/TTL DC specifications, transmitter inputs, receiver outputs, control pins |
| Low Level Input Voltage | GND min, 0.8 max V; CMOS/TTL DC specifications |
| High Level Output Voltage | 2.7 min, 2.9 typ V; IOH=-0.4 mA |
| High Level Output Voltage | 2.7 min, 2.85 typ V; IOH=-2 mA |
| Low Level Output Voltage | 0.1 typ, 0.3 max V; IOL=2 mA |
| Input Clamp Voltage | -0.79 typ, -1.5 max V; ICL=-18 mA |
| Input Current | +1.8 typ, +15 max µA; VIN=0.4 V, 2.5 V, or VCC |
| Input Current | -15 min, 0 typ µA; VIN=GND |
| Output Short Circuit Current | -120 mA; VOUT=0 V, CMOS/TTL output |
| LVDS Differential Output Voltage | 250 min, 345 typ, 450 max mV; RL=100 Ω |
| LVDS Change in Differential Output Voltage | 35 max mV; between complementary output states |
| LVDS Offset Voltage | 1.125 min, 1.25 typ, 1.375 max V; LVDS driver DC specifications |
| LVDS Change in Offset Voltage | 35 max mV; between complementary output states |
| LVDS Output Short Circuit Current | -3.5 typ, -10 max mA; VOUT=0 V, RL=100 Ω |
| LVDS Output TRI-STATE Current | ±1 typ, ±10 max µA; PD=0 V, VOUT=0 V or VCC |
| LVDS Receiver Differential Input High Threshold | +100 max mV; VCM=+1.2 V |
| LVDS Receiver Differential Input Low Threshold | -100 min mV; LVDS receiver DC specifications |
| LVDS Receiver Input Current | ±10 max µA; VIN=+2.4 V, VCC=3.6 V |
| Transmitter Supply Current Worst Case | 91.4 typ, 140 max mA; RL=100 Ω, CL=5 pF, f=32.5 MHz, worst case pattern, DUAL=High, BAL=High |
| Transmitter Supply Current Worst Case | 155 typ, 210 max mA; RL=100 Ω, CL=5 pF, f=112 MHz, worst case pattern, DUAL=High, BAL=High |
| Transmitter Power Down Supply Current | 4.8 typ, 50 max µA; PD=Low, driver outputs in TRI-STATE |
| TxCLKIN Transition Time | 1.0 min, 2.0 typ, 3.0 max ns; DUAL=GND or VCC |
| TxCLKIN Period | 8.928 min, 30.77 max ns; DUAL=GND or VCC |
| LVDS Low-to-High Transition Time | 0.14 typ, 0.7 max ns; PRE=0.75 V disabled |
| LVDS High-to-Low Transition Time | 0.16 typ, 0.8 max ns; PRE=0.75 V disabled |
| Transmitter Output Bit Width | 1/7 TCIP ns; DUAL=GND or VCC |
| TxOUT Channel-to-Channel Skew | 100 max ps; transmitter switching characteristics |
| TxIN Setup to TxCLKIN | 2.7 min ns; transmitter switching characteristics |
| TxIN Hold to TxCLKIN | 0 min ns; transmitter switching characteristics |
| Transmitter PLL Set Time | 10 max ms; transmitter switching characteristics |
| Transmitter Powerdown Delay | 100 max ns; transmitter switching characteristics |
| Maximum Dual Pixel Clock Rate | 112 MHz; dual pixel 48-bit RGB mode |
| Maximum Single Pixel Input Clock Rate | 170 MHz; 24-bit color single pixel input mode with single-to-dual pixel conversion |
| LVDS Data Line Speed | 672 Mbps; maximum dual pixel rate of 112 MHz |
| Total Throughput | 5.38 Gbps; at maximum dual pixel rate |
| LVDS Output Streams | 8 data streams; transmitter converts 48 bits of CMOS/TTL data to LVDS |
| Cable Deskew Range | ±1 LVDS data bit time; up to 80 MHz clock rate, receiver inputs |
| Intra-Pair Skew Tolerance | 300 ps; receiver input skew tolerance |
| Datasheet Status | request_only |
Product Overview
The DS90C387 is a Texas Instruments dual pixel LVDS display interface transmitter for Signal_Chain designs. It converts 48 bits of CMOS/TTL data into eight LVDS data streams and supports dual pixel 48-bit RGB operation at clock rates up to 112 MHz. In 24-bit color single pixel input mode, it supports single-to-dual pixel conversion with input clock rates up to 170 MHz.
Recommended operation is specified from a 3.0 V to 3.6 V supply, with 3.3 V typical operation, across -10°C to +70°C free-air temperature. The receiver input range is 0 V to 2.4 V, and recommended supply noise is limited to 100 mV p-p. LVDS output performance includes 250 mV minimum, 345 mV typical, and 450 mV maximum differential output voltage into 100 Ω.
The device is supplied in a 100 TQFP package. Package data includes 2.8 W dissipation at TA=25°C and derating of 18.2 mW/°C above +25°C. Display interface use cases are supported by 672 Mbps LVDS data line speed, 5.38 Gbps total throughput, receiver cable deskew of ±1 LVDS data bit time up to 80 MHz, and 300 ps intra-pair skew tolerance.
Key Features
- Converts 48-bit CMOS/TTL data into eight LVDS streams
- Supports 112 MHz dual pixel 48-bit RGB operation
- Supports 170 MHz single pixel input clock conversion
- Delivers 672 Mbps LVDS data line speed
- Provides 5.38 Gbps total throughput at maximum rate
- Operates from 3.0 V to 3.6 V supply
- LVDS differential output voltage from 250 mV to 450 mV
- Receiver cable deskew range of ±1 LVDS bit time
- Receiver input intra-pair skew tolerance is 300 ps
- Power-down supply current is 4.8 µA typical
Typical Applications
- Dual pixel LVDS display links
- 48-bit RGB display interfaces
- CMOS/TTL to LVDS transmission
- Single-to-dual pixel conversion
- High-throughput panel connections
- Deskewed receiver input links
- 100 TQFP display interface assemblies
Procurement Notes
When requesting a quote for DS90C387, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What supply range is specified for the DS90C387?
The DS90C387 recommended operating supply voltage is 3.0 V minimum, 3.3 V typical, and 3.6 V maximum. The recommended free-air operating temperature range is -10°C to +70°C.
What display data rates does the DS90C387 support?
The device supports a maximum dual pixel clock rate of 112 MHz in dual pixel 48-bit RGB mode. At that rate, the LVDS data line speed is 672 Mbps and total throughput is 5.38 Gbps.
How many LVDS streams are provided by the DS90C387?
The DS90C387 converts 48 bits of CMOS/TTL data to LVDS and provides eight LVDS data streams. Its LVDS differential output voltage is specified from 250 mV minimum to 450 mV maximum with a 345 mV typical value into 100 Ω.
What package and thermal data are listed for DS90C387?
The DS90C387 is listed in a 100 TQFP package. Package power dissipation is 2.8 W at TA=25°C, with package derating of 18.2 mW/°C above +25°C for the 100 TQFP package.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.